Commit Graph

9 Commits

Author SHA1 Message Date
David Anderson 2cd172cc73 tasks.py: add sim directory when running tests
So that bluesim can find the DP16KD simulation model.
2024-08-31 00:00:59 -07:00
David Anderson a4a10becbf tasks.py: print one more intermediate output path 2024-08-30 20:06:36 -07:00
David Anderson 5d16ce23aa tasks.py: adjust yosys script 2024-08-23 00:20:31 -07:00
David Anderson 2a8689564c tasks.py: remove debug message 2024-08-20 09:13:36 -07:00
David Anderson 5df41d4b94 lib: use DelayLine in ECP5_RAM
Cleans up the code nicely, and still produces the correct logic.
2024-08-20 00:54:50 -07:00
David Anderson 85e27554ec lib: add a DelayLine module
A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
2024-08-19 23:00:15 -07:00
David Anderson db30e4a23f tasks.py: prettify output, support running partial synthesis
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
2024-08-17 15:41:21 -07:00
David Anderson dad128b56b Fix up some bugs in the Invoke script. 2024-08-15 00:22:30 -07:00
David Anderson e83f3a993c add a simple build/test script 2024-08-14 09:39:42 -07:00