4 Commits

Author	SHA1	Message	Date
David Anderson	1ccd1b0072	lib/DelayLine: add a bit more documentation	2024-08-20 09:15:52 -07:00
David Anderson	5df41d4b94	lib: use DelayLine in ECP5_RAM ... Cleans up the code nicely, and still produces the correct logic.	2024-08-20 00:54:50 -07:00
David Anderson	f1e705fd31	lib: add more documentation	2024-08-20 00:29:32 -07:00
David Anderson	85e27554ec	lib: add a DelayLine module ... A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.	2024-08-19 23:00:15 -07:00