Experiment comparing bsc-contrib's video timing generator with brute force
Brute force is a naively written state machine that combines both horizontal and vertical timings into one, in a way that unrolls comically badly. It's obviously uncompetitive as-is, but I wanted to use that as a starting point to see how much bsc and yosys would still be able to cope with it. The result: the worse code takes much longer for bluespec to evaluate, and it consumes ~4x the amount of logic elements after synthesis. Less terrible than I expected, to be honest!
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// This code is derived from the video sync generator at
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// https://github.com/B-Lang-org/bsc-contrib/blob/main/Libraries/FPGA/Misc/Video.bsv,
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// simplified down to serve as an experiment/comparison of synthesis
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// efficiency with the sibling directory that has a more imperative
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// construction (and also worse, it tursn out).
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package Top;
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import Counter::*;
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import StmtFSM::*;
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typedef struct {
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Integer active;
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Integer fporch;
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Integer sync;
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Integer bporch;
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} SyncDescriptor;
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SyncDescriptor horizontal = SyncDescriptor{
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active: 640,
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fporch: 16,
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sync: 96,
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bporch: 48
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};
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SyncDescriptor vertical = SyncDescriptor{
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active: 480,
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fporch: 10,
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sync: 2,
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bporch: 33
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};
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interface SyncGenerator;
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method Action tick();
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method Bool preedge();
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method Bool out_n();
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method Bool out();
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method Bool active();
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endinterface
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module mkSyncGenerator#(SyncDescriptor info)(SyncGenerator);
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let maxActive = fromInteger(info.active - 1);
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let maxFPorch = fromInteger(info.fporch - 1);
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let maxSync = fromInteger(info.sync - 1);
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let maxBPorch = fromInteger(info.bporch - 1);
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/////////////////////
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/// Design Elements
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/////////////////////
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Counter#(16) rCounter <- mkCounter(0);
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PulseWire pwTick <- mkPulseWire;
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PulseWire pwPreSyncEdge <- mkPulseWire;
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Reg#(Bool) rSyncOut <- mkReg(True);
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Reg#(Bool) rActive <- mkReg(False);
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/////////////////////
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/// Rules
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/////////////////////
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Stmt machine =
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seq
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while(True) seq
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// Front Porch
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while(rCounter.value < maxFPorch) action
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rCounter.up;
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endaction
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action
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rCounter.clear;
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pwPreSyncEdge.send;
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rSyncOut <= False;
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rActive <= False;
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endaction
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// Sync Pulse
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while(rCounter.value < maxSync) action
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rCounter.up;
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endaction
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action
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rCounter.clear;
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rSyncOut <= True;
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rActive <= False;
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endaction
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// Back Porch
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while(rCounter.value < maxBPorch) action
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rCounter.up;
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endaction
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action
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rCounter.clear;
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rSyncOut <= True;
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rActive <= True;
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endaction
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// Active
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while(rCounter.value < maxActive) action
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rCounter.up;
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endaction
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action
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rCounter.clear;
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rSyncOut <= True;
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rActive <= False;
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endaction
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endseq
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endseq;
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FSM fsmSyncGen <- mkFSMWithPred(machine, pwTick);
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rule start_sync_generator(fsmSyncGen.done);
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fsmSyncGen.start;
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endrule
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method Action tick = pwTick.send;
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method Bool preedge = pwPreSyncEdge;
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method Bool out_n = rSyncOut;
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method Bool out = !rSyncOut;
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method Bool active = rActive;
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endmodule: mkSyncGenerator
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interface ITop;
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(* always_ready *)
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method Bool paint();
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(* always_ready *)
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method Bool hsync();
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(* always_ready *)
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method Bool vsync();
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endinterface
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(* synthesize *)
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module mkTop (ITop);
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let horiz <- mkSyncGenerator(horizontal);
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let vert <- mkSyncGenerator(vertical);
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(* no_implicit_conditions, fire_when_enabled *)
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rule advance_horizontal;
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horiz.tick;
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule advance_vertical (horiz.preedge);
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vert.tick;
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endrule
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method Bool paint = horiz.active && vert.active;
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method Bool hsync = horiz.out;
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method Bool vsync = vert.out;
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endmodule
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endpackage
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@ -0,0 +1,28 @@
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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## LED indicators "blinkey" and "gpio" sheet
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LOCATE COMP "paint" SITE "H3";
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LOCATE COMP "hsync" SITE "E1";
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LOCATE COMP "vsync" SITE "E2";
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IOBUF PORT "paint" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "hsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "vsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "uart_rx_v" SITE "M1"; # FIRE1
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IOBUF PORT "uart_rx_v" PULLMODE=UP IO_TYPE=LVCMOS33;
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LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
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IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "wifi_gpio0" SITE "L2";
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IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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@ -0,0 +1,108 @@
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package Top;
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import Counter::*;
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import StmtFSM::*;
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typedef struct {
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Integer active;
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Integer fporch;
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Integer sync;
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Integer bporch;
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} SyncDescriptor;
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SyncDescriptor horizontal = SyncDescriptor{
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active: 640,
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fporch: 16,
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sync: 96,
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bporch: 48
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};
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SyncDescriptor vertical = SyncDescriptor{
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active: 480,
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fporch: 10,
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sync: 2,
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bporch: 33
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};
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interface SyncGenerator;
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method Action tick();
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method Bool preedge();
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method Bool out_n();
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method Bool out();
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method Bool active();
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endinterface
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interface ITop;
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(* always_ready *)
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method Bool paint();
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(* always_ready *)
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method Bool hsync();
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(* always_ready *)
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method Bool vsync();
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endinterface
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(* synthesize *)
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module mkTop (ITop);
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Reg#(Bool) rPaint <- mkReg(False);
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Reg#(Bool) rHsync <- mkReg(False);
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Reg#(Bool) rVsync <- mkReg(False);
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let blank_line_fsm = seq
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// Sync pulse
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repeat (96) rHsync <= True;
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// Back porch
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repeat (48) rHsync <= False;
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// Visible area
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repeat (640) noAction;
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// Front porch
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repeat (16) noAction;
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endseq;
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let video_line_fsm = seq
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// Sync pulse
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repeat (96) rHsync <= True;
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// Back porch
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repeat (48) rHsync <= False;
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// Visible area
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repeat (640) rPaint <= True;
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// Front porch
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repeat (16) rPaint <= False;
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endseq;
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let frame_fsm = seq
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while (True) seq
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// Sync pulse
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repeat (2) par
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rVsync <= True;
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blank_line_fsm;
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endpar
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// Back porch
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repeat (33) par
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rVsync <= False;
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blank_line_fsm;
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endpar
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// Visible area
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repeat (480) video_line_fsm;
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// Front porch
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repeat (10) blank_line_fsm;
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endseq
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endseq;
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let fsm <- mkFSM(frame_fsm);
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rule run_timing (fsm.done());
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fsm.start();
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endrule
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method Bool paint = rPaint._read;
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method Bool hsync = rHsync._read;
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method Bool vsync = rVsync._read;
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endmodule
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endpackage
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@ -0,0 +1,28 @@
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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## LED indicators "blinkey" and "gpio" sheet
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LOCATE COMP "paint" SITE "H3";
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LOCATE COMP "hsync" SITE "E1";
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LOCATE COMP "vsync" SITE "E2";
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IOBUF PORT "paint" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "hsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "vsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "uart_rx_v" SITE "M1"; # FIRE1
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IOBUF PORT "uart_rx_v" PULLMODE=UP IO_TYPE=LVCMOS33;
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LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
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IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "wifi_gpio0" SITE "L2";
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IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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