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lib: default clocks and resets to the ambient ones from context 

Callers can still specify whacky cross-domain RAMs in the cfg, but the
default is what you usually want: a dual-port RAM with both ports in the
caller's clock/reset domain.
This commit is contained in:
David Anderson 2024-08-13 20:53:47 -07:00
parent e64b990f80
commit a23661a449
1 changed files with 32 additions and 8 deletions
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40
lib/ECP5_RAM.bsv
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@ -17,8 +17,12 @@ typedef enum {
// ECP5_EBRPortConfig is the static configuration of an EBR port. // ECP5_EBRPortConfig is the static configuration of an EBR port.
typedef struct { typedef struct {
Clock clk; // clk, if specified, is the Clock to use for the port. If
Reset rstN; // unspecified, uses the module default clock.
Maybe#(Clock) clk;
// rstN, if specified, is the Reset to use for the port. If
// unspecified, uses the module default reset.
Maybe#(Reset) rstN;
// By default, ECP5 EBRs only register the input address and write // By default, ECP5 EBRs only register the input address and write
// data, giving a 1-cycle latency for operations. If // data, giving a 1-cycle latency for operations. If
// registered_output is true, the output value is also registered, // registered_output is true, the output value is also registered,
@ -34,8 +38,8 @@ typedef struct {
instance DefaultValue#(ECP5_EBRPortConfig); instance DefaultValue#(ECP5_EBRPortConfig);
defaultValue = ECP5_EBRPortConfig{ defaultValue = ECP5_EBRPortConfig{
clk: noClock, clk: defaultValue,
rstN: noReset, rstN: defaultValue,
registered_output: False, registered_output: False,
chip_select_addr: 0, chip_select_addr: 0,
write_mode: Normal write_mode: Normal
@ -68,14 +72,34 @@ import "BVI" ECP5_RAM =
Integer portB_width) Integer portB_width)
(ECP5_EBRCoreInner); (ECP5_EBRCoreInner);
let defClk <- exposeCurrentClock;
let defRstN <- exposeCurrentReset;
let portA_bsv_clock = case (port_a.clk) matches
tagged Invalid: defClk;
tagged Valid .clk: clk;
endcase;
let portA_bsv_rstN = case (port_a.rstN) matches
tagged Invalid: defRstN;
tagged Valid .rstN: rstN;
endcase;
let portB_bsv_clock = case (port_b.clk) matches
tagged Invalid: defClk;
tagged Valid .clk: clk;
endcase;
let portB_bsv_rstN = case (port_b.rstN) matches
tagged Invalid: defRstN;
tagged Valid .rstN: rstN;
endcase;
default_clock no_clock; default_clock no_clock;
default_reset no_reset; default_reset no_reset;
input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = port_a.clk; input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = portA_bsv_clock;
input_reset portA_rstN(RSTA) clocked_by(portA_clk) = port_a.rstN; input_reset portA_rstN(RSTA) clocked_by(portA_clk) = portA_bsv_rstN;
input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = port_b.clk; input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = portB_bsv_clock;
input_reset portB_rstN(RSTB) clocked_by(portB_clk) = port_b.rstN; input_reset portB_rstN(RSTB) clocked_by(portB_clk) = portB_bsv_rstN;
parameter DATA_WIDTH_A = portA_width; parameter DATA_WIDTH_A = portA_width;
parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG"; parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG";