From 913c407224c59e60e05907b92b30eefcf9f18275 Mon Sep 17 00:00:00 2001 From: David Anderson Date: Sun, 8 Sep 2024 15:15:32 -0700 Subject: [PATCH] hardware/sentinel65x: comment out logic I'm not quite ready to define top-levels yet, and having this incomplete code here makes 'inv build .' fail. --- hardware/sentinel65x/Top.bsv | 88 ++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/hardware/sentinel65x/Top.bsv b/hardware/sentinel65x/Top.bsv index dafcac3..90f5b37 100644 --- a/hardware/sentinel65x/Top.bsv +++ b/hardware/sentinel65x/Top.bsv @@ -1,57 +1,57 @@ package Top; -import Connectable::*; -import TriState::*; +// import Connectable::*; +// import TriState::*; -import ClockOut::*; -import PLL::*; +// import ClockOut::*; +// import PLL::*; -interface SystemBus; - (* always_enabled,prefix="" *) - method Action addr(UInt#(24) addr); - (* always_enabled,prefix="" *) - method Action phi2(bit phi2); - (* always_enabled,prefix="" *) - method Action write(bit we); -endinterface +// interface SystemBus; +// (* always_enabled,prefix="" *) +// method Action addr(UInt#(24) addr); +// (* always_enabled,prefix="" *) +// method Action phi2(bit phi2); +// (* always_enabled,prefix="" *) +// method Action write(bit we); +// endinterface -module mkSystemBus(SystemBus); +// module mkSystemBus(SystemBus); -endmodule +// endmodule -interface Top; - (* always_ready *) - method bit clkout(); +// interface Top; +// (* always_ready *) +// method bit clkout(); - interface SystemBus cpu; -endinterface +// interface SystemBus cpu; +// endinterface -(* synthesize,no_default_clock,no_default_reset,default_gate_unused *) -module mkTop(Clock clk_ref, - (* clocked_by="no_clock" *) Reset rst, - (* clocked_by="no_clock" *) Inout#(Bit#(8)) data, - Top ifc); - let pll <- mkPLL(clk_ref); - let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst)); +// (* synthesize,no_default_clock,no_default_reset,default_gate_unused *) +// module mkTop(Clock clk_ref, +// (* clocked_by="no_clock" *) Reset rst, +// (* clocked_by="no_clock" *) Inout#(Bit#(8)) data, +// Top ifc); +// let pll <- mkPLL(clk_ref); +// let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst)); - Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst)); - Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst)); - TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst)); - mkConnection(data, data_in.io); +// Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst)); +// Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst)); +// TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst)); +// mkConnection(data, data_in.io); - interface SystemBus cpu; - method clkout = cpu_clk.value; - method Action addr(a); - noAction; - endmethod - method Action phi2(v); - noAction; - endmethod - method Action write(bit we); - noAction; - endmethod - //interface data = data_in.io; - endinterface -endmodule +// interface SystemBus cpu; +// method clkout = cpu_clk.value; +// method Action addr(a); +// noAction; +// endmethod +// method Action phi2(v); +// noAction; +// endmethod +// method Action write(bit we); +// noAction; +// endmethod +// //interface data = data_in.io; +// endinterface +// endmodule endpackage