diff --git a/vram/MemoryArbiter.bsv b/vram/MemoryArbiter.bsv
index 6f262b0..5029bfd 100644
--- a/vram/MemoryArbiter.bsv
+++ b/vram/MemoryArbiter.bsv
@@ -7,9 +7,9 @@ export MemoryArbiterReader(..);
 export MemoryArbiter(..);
 export mkMemoryArbiter;
 
-// A MemoryArbiterWriter can request use of a memory port to write to
-// an address. When a request is feasible, grant() returns True in the
-// same cycle.
+// A MemoryArbiterWriter can request use of a memory port to read or
+// write to an address. When a request is feasible, grant() returns
+// True in the same cycle.
 (* always_ready *)
 interface MemoryArbiterWriter#(type addr);
    method Action request(Bool write, addr address);
@@ -26,8 +26,7 @@ interface MemoryArbiterReader#(type addr);
 endinterface
 
 // A MemoryArbiter manages concurrent access to memory ports. It
-// mediates access between 2 writers and 4 readers, which are
-// statically allocated to one of 2 internal memory ports.
+// mediates access between 2 writers and 4 readers.
 interface MemoryArbiter#(type addr);
    // Assigned to port A.
    interface MemoryArbiterWriter#(addr) cpu;