adjust 'inv genclk' to allow per-hardware PLLs
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parent
77b772c7ee
commit
6e84e9c689
4
tasks.py
4
tasks.py
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@ -235,8 +235,8 @@ def clean(c):
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shutil.rmtree("out")
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shutil.rmtree("out")
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@task
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@task
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def genclk(c, in_mhz=25, main_mhz=100, cpu_mhz=10, vga_mhz=25):
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def genclk(c, hardware_name, in_mhz=25, main_mhz=100, cpu_mhz=8, vga_mhz=25):
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out = Path("sentinel65x/PLL.v")
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out = Path(f"hardware/{hardware_name}/PLL.v")
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c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
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c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
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bsv_out = out.with_suffix(".bsv")
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bsv_out = out.with_suffix(".bsv")
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with open(bsv_out) as f:
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with open(bsv_out) as f:
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