From 5e997201db36ed7fd878915f8bb9a9d45cbe31f4 Mon Sep 17 00:00:00 2001 From: David Anderson Date: Fri, 6 Sep 2024 21:08:51 -0700 Subject: [PATCH] hardware/sentinel65x: move top-level hw module to hw subdir --- {sentinel65x => hardware/sentinel65x}/PLL.bsv | 0 {sentinel65x => hardware/sentinel65x}/PLL.v | 0 hardware/sentinel65x/Top.bsv | 57 +++++++++++++++++++ 3 files changed, 57 insertions(+) rename {sentinel65x => hardware/sentinel65x}/PLL.bsv (100%) rename {sentinel65x => hardware/sentinel65x}/PLL.v (100%) create mode 100644 hardware/sentinel65x/Top.bsv diff --git a/sentinel65x/PLL.bsv b/hardware/sentinel65x/PLL.bsv similarity index 100% rename from sentinel65x/PLL.bsv rename to hardware/sentinel65x/PLL.bsv diff --git a/sentinel65x/PLL.v b/hardware/sentinel65x/PLL.v similarity index 100% rename from sentinel65x/PLL.v rename to hardware/sentinel65x/PLL.v diff --git a/hardware/sentinel65x/Top.bsv b/hardware/sentinel65x/Top.bsv new file mode 100644 index 0000000..dafcac3 --- /dev/null +++ b/hardware/sentinel65x/Top.bsv @@ -0,0 +1,57 @@ +package Top; + +import Connectable::*; +import TriState::*; + +import ClockOut::*; +import PLL::*; + +interface SystemBus; + (* always_enabled,prefix="" *) + method Action addr(UInt#(24) addr); + (* always_enabled,prefix="" *) + method Action phi2(bit phi2); + (* always_enabled,prefix="" *) + method Action write(bit we); +endinterface + +module mkSystemBus(SystemBus); + +endmodule + +interface Top; + (* always_ready *) + method bit clkout(); + + interface SystemBus cpu; +endinterface + +(* synthesize,no_default_clock,no_default_reset,default_gate_unused *) +module mkTop(Clock clk_ref, + (* clocked_by="no_clock" *) Reset rst, + (* clocked_by="no_clock" *) Inout#(Bit#(8)) data, + Top ifc); + let pll <- mkPLL(clk_ref); + let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst)); + + Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst)); + Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst)); + TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst)); + mkConnection(data, data_in.io); + + interface SystemBus cpu; + method clkout = cpu_clk.value; + method Action addr(a); + noAction; + endmethod + method Action phi2(v); + noAction; + endmethod + method Action write(bit we); + noAction; + endmethod + //interface data = data_in.io; + endinterface +endmodule + +endpackage