vram/MemArbiter: fix bug with write conflict avoidance
Now that all arbiter ports can request to write, arbitration must check both (write, read) and (read, write) conflicts, not just (write, read).
This commit is contained in:
parent
191cd1bfa2
commit
519eddc552
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@ -4,6 +4,7 @@ import MemArbiter::*;
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import Vector::*;
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import DReg::*;
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import DelayLine::*;
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import Connectable::*;
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typedef UInt#(2) Addr;
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@ -22,70 +23,51 @@ endinterface
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(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
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module mkTop(Top);
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Vector#(2, Reg#(Maybe#(MemArbiterWrite#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));
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Vector#(6, Reg#(Maybe#(MemArbiterOp#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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MemArbiter#(Addr) ret <- mkMemArbiter();
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MemArbiter#(3, Addr) portA <- mkPriorityMemArbiter();
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MemArbiter#(3, Addr) portB <- mkRoundRobinMemArbiter();
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mkConnection(portA, portB);
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let arbiters = append(portA.ports, portB.ports);
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Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
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rule req_cpu (wrin[0] matches tagged Valid .req);
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ret.cpu.request(req);
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endrule
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rule req_debugger (wrin[1] matches tagged Valid .req);
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ret.debugger.request(req);
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endrule
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rule req_palette (rdin[0] matches tagged Valid .addr);
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ret.palette.request(addr);
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endrule
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rule req_tile1 (rdin[1] matches tagged Valid .addr);
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ret.tile1.request(addr);
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endrule
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rule req_tile2 (rdin[2] matches tagged Valid .addr);
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ret.tile2.request(addr);
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endrule
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rule req_sprite (rdin[3] matches tagged Valid .addr);
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ret.sprite.request(addr);
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endrule
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for (Integer i=0; i<6; i=i+1) begin
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rule req (wrin[i] matches tagged Valid .req);
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arbiters[i].request(req);
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endrule
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end
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rule resp;
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Vector#(6, Bool) r = newVector;
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r[0] = ret.cpu.grant();
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r[1] = ret.debugger.grant();
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r[2] = ret.palette.grant();
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r[3] = ret.tile1.grant();
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r[4] = ret.tile2.grant();
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r[5] = ret.sprite.grant();
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ok <= r;
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function Bool get(MemArbiterServer#(Addr) s);
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return s.grant();
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endfunction
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ok <= map(get, arbiters);
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endrule
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method Action cpu(Bool write, Addr addr);
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wrin[0] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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wrin[0] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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endmethod
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method Action debugger(Bool write, Addr addr);
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wrin[1] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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wrin[1] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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endmethod
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method Action palette(Addr addr);
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rdin[0] <= tagged Valid addr;
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wrin[2] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action tile1(Addr addr);
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rdin[1] <= tagged Valid addr;
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wrin[3] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action tile2(Addr addr);
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rdin[2] <= tagged Valid addr;
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wrin[4] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action sprite(Addr addr);
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rdin[3] <= tagged Valid addr;
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wrin[5] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Bit#(6) grants();
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@ -15,6 +15,15 @@ typedef struct {
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addr addr;
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} MemArbiterOp#(type addr) deriving (Bits, Eq, FShow);
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function Bool mem_ops_conflict(Maybe#(MemArbiterOp#(addr)) a, Maybe#(MemArbiterOp#(addr)) b)
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provisos(Eq#(addr));
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if (a matches tagged Valid .ar &&& b matches tagged Valid .br &&& ar.addr == br.addr)
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return ar.write || br.write;
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else
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return False;
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endfunction
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// A MemArbiterServer receives requests and emits grants.
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interface MemArbiterServer#(type addr);
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method Action request(MemArbiterOp#(addr) req);
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@ -54,22 +63,23 @@ interface MemArbiter#(numeric type num_clients, type addr);
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// each memory port must cooperate to avoid simultaneously granting
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// conflicting requests from their clients.
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//
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// Calling forbid_addr prevents the arbiter from granting a
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// concurrent request to access the given address. forbidden_addr
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// emits the address for which a write access is being granted.
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// Calling conflict prevents the arbiter from granting a concurrent
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// request that would result in a write-write, read-write or
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// write-read conflict. granted_op emits the operation that the
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// arbiter is granting, if any.
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//
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// MemArbiter intances are Connectable: mkConnection(a, b) gives
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// conflict priority to a. That is, b will not grant requests that
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// conflict with the grant that a has emitted.
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method Action forbid_addr(addr addr);
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method addr forbidden_addr();
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// conflict priority to a. That is, b only grants requests that
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// don't conflict with a's grant.
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method Action conflict(MemArbiterOp#(addr) conflict);
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method MemArbiterOp#(addr) granted_op();
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endinterface
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instance Connectable#(MemArbiter#(m, addr), MemArbiter#(n, addr));
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module mkConnection(MemArbiter#(m, addr) a, MemArbiter#(n, addr) b, Empty ifc);
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(* fire_when_enabled *)
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rule forward_forbid;
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b.forbid_addr(a.forbidden_addr);
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rule forward_conflict;
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b.conflict(a.granted_op);
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endrule
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endmodule
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endinstance
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@ -84,12 +94,8 @@ module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire());
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(addr) blocked_in <- mkRWire();
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RWire#(addr) blocked_out <- mkRWire();
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function Bool is_blocked(addr addr);
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return blocked_in.wget() == tagged Valid addr;
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endfunction
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RWire#(MemArbiterOp#(addr)) conflict_in <- mkRWire();
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RWire#(MemArbiterOp#(addr)) granted_op_out <- mkRWire();
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(* no_implicit_conditions, fire_when_enabled *)
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rule grant_requests;
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@ -97,12 +103,13 @@ module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
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Bool done = False;
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for (Integer i=0; i<valueOf(num_clients); i=i+1) begin
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if (reqs[i].wget() matches tagged Valid .req &&& !is_blocked(req.addr) &&& !done) begin
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done = True;
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grant[i] = True;
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if (req.write)
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blocked_out.wset(req.addr);
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end
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if (reqs[i].wget() matches tagged Valid .req &&&
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!mem_ops_conflict(conflict_in.wget(), reqs[i].wget()) &&&
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!done) begin
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done = True;
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grant[i] = True;
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granted_op_out.wset(req);
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end
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end
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grants <= grant;
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@ -116,9 +123,9 @@ module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
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endinterface);
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interface ports = _ifcs;
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method forbid_addr = blocked_in.wset;
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method addr forbidden_addr() if (blocked_out.wget() matches tagged Valid .addr);
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return addr;
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method conflict = conflict_in.wset;
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method MemArbiterOp#(addr) granted_op() if (granted_op_out.wget() matches tagged Valid .op);
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return op;
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endmethod
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endmodule
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@ -126,19 +133,15 @@ typedef struct {
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Bool granted;
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Vector#(n, Bool) grant_vec;
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UInt#(TLog#(n)) selected;
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Maybe#(addr) blocked_addr;
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Maybe#(MemArbiterOp#(addr)) granted_op;
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} GrantResult#(numeric type n, type addr) deriving (Bits, Eq, FShow);
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// select_grant computes which one entry of requests should be granted.
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function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr))) requests,
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UInt#(TLog#(n)) hipri,
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Maybe#(addr) block_addr)
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Maybe#(MemArbiterOp#(addr)) conflict)
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provisos (Eq#(addr));
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function is_blocked(addr);
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return tagged Valid addr == block_addr;
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endfunction
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function onehot(idx);
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let ret = replicate(False);
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ret[idx] = True;
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@ -149,12 +152,12 @@ function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr
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Tuple2#(UInt#(TLog#(n)),
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Maybe#(MemArbiterOp#(addr))) next);
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match {.idx, .mreq} = next;
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if (mreq matches tagged Valid .req &&& !acc.granted &&& !is_blocked(req.addr))
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if (mreq matches tagged Valid .req &&& !acc.granted &&& !mem_ops_conflict(conflict, mreq))
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return GrantResult{
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granted: True,
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grant_vec: onehot(idx),
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selected: idx,
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blocked_addr: req.write ? tagged Valid req.addr : tagged Invalid
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granted_op: tagged Valid req
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};
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else
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// Previous grant won, not requesting, or request not satisfiable.
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@ -167,7 +170,7 @@ function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr
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granted: False,
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grant_vec: replicate(False),
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selected: 0,
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blocked_addr: tagged Invalid
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granted_op: tagged Invalid
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};
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return foldl(do_fold, seed, rot);
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endfunction
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@ -180,8 +183,8 @@ module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire);
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(addr) blocked_in <- mkRWire();
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Wire#(Maybe#(addr)) blocked_out <- mkBypassWire();
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RWire#(MemArbiterOp#(addr)) conflict_in <- mkRWire();
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RWire#(MemArbiterOp#(addr)) granted_op_out <- mkRWire();
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// high_prio is the index of the client that should be first in
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// line to receive access. Every time we grant access to a client,
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@ -195,7 +198,7 @@ module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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rule grant;
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let in = map(get_mreq, reqs);
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let res = select_grant(in, high_prio, blocked_in.wget());
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let res = select_grant(in, high_prio, conflict_in.wget());
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grants <= res.grant_vec;
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if (res.granted)
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@ -203,7 +206,8 @@ module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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high_prio <= 0;
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else
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high_prio <= res.selected+1;
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blocked_out <= res.blocked_addr;
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if (res.granted_op matches tagged Valid .op)
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granted_op_out.wset(op);
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endrule
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Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
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@ -214,9 +218,9 @@ module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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endinterface);
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interface ports = _ifcs;
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method forbid_addr = blocked_in.wset;
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method addr forbidden_addr() if (blocked_out matches tagged Valid .addr);
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return addr;
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method conflict = conflict_in.wset;
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method MemArbiterOp#(addr) granted_op() if (granted_op_out.wget() matches tagged Valid .op);
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return op;
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endmethod
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endmodule
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@ -16,10 +16,10 @@ typedef struct {
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String name;
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Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs;
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Maybe#(Addr) forbid_addr;
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Maybe#(MemArbiterOp#(Addr)) conflict;
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Vector#(n, Bool) want_grants;
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Maybe#(Addr) want_forbid_addr;
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Maybe#(MemArbiterOp#(Addr)) want_granted_op;
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} TestCase#(numeric type n) deriving (Bits, Eq);
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function Maybe#(MemArbiterOp#(Addr)) read(Addr addr);
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@ -34,14 +34,10 @@ function Maybe#(MemArbiterOp#(Addr)) idle();
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return tagged Invalid;
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endfunction
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function Maybe#(Addr) noForbid();
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function Maybe#(MemArbiterOp#(Addr)) noConflict();
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return tagged Invalid;
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endfunction
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function Maybe#(Addr) forbid(Addr a);
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return tagged Valid a;
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endfunction
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function Vector#(n, Bool) grant(Integer granted);
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function gen(idx);
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return idx == granted;
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@ -56,15 +52,15 @@ endfunction
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function TestCase#(n) testCase(String name,
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Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs,
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Maybe#(Addr) forbid_addr,
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Maybe#(MemArbiterOp#(Addr)) conflict,
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Vector#(n, Bool) want_grants,
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Maybe#(Addr) want_forbid_addr);
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Maybe#(MemArbiterOp#(Addr)) want_granted_op);
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return TestCase{
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name: name,
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reqs: reqs,
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forbid_addr: forbid_addr,
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conflict: conflict,
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want_grants: want_grants,
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want_forbid_addr: want_forbid_addr
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want_granted_op: want_granted_op
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};
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endfunction
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@ -87,15 +83,15 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
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end
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(* no_implicit_conditions, fire_when_enabled *)
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rule forbid (running && isValid(tests[idx].forbid_addr));
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dut.forbid_addr(validValue(tests[idx].forbid_addr));
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rule forbid (running && isValid(tests[idx].conflict));
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dut.conflict(validValue(tests[idx].conflict));
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endrule
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Wire#(Maybe#(Addr)) got_forbid_addr <- mkDWire(tagged Invalid);
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Wire#(Maybe#(MemArbiterOp#(Addr))) got_granted_op <- mkDWire(tagged Invalid);
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(* fire_when_enabled *)
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rule collect_forbid (running);
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got_forbid_addr <= tagged Valid dut.forbidden_addr();
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rule collect_granted_op (running);
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got_granted_op <= tagged Valid dut.granted_op();
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endrule
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function Fmt req_s(Maybe#(MemArbiterOp#(Addr)) v);
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@ -106,36 +102,29 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
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endcase
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endfunction
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function Fmt addr_s(Maybe#(Addr) v);
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case (v) matches
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tagged Invalid: return $format("<nil>");
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tagged Valid .a: return $format("%0d", a);
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endcase
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endfunction
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(* no_implicit_conditions, fire_when_enabled *)
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rule check (running);
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let test = tests[idx];
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let reqs = test.reqs;
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let want_grants = test.want_grants;
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let want_forbid_addr = test.want_forbid_addr;
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let want_granted_op = test.want_granted_op;
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Vector#(n, Bool) got_grants = newVector;
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for (Integer i=0; i<valueOf(n); i=i+1)
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got_grants[i] = dut.ports[i].grant();
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$display("RUN %s (%0d)", tests[idx].name, idx);
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if (got_grants != want_grants || got_forbid_addr != want_forbid_addr) begin
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if (got_grants != want_grants || got_granted_op != want_granted_op) begin
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$display("input:");
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for (Integer i=0; i<valueOf(n); i=i+1)
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$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
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$display(" forbid: ", addr_s(test.forbid_addr));
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$display(" conflict: ", fshow(test.conflict));
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$display(" output:");
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$display(" grants: ", fshow(got_grants));
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$display(" forbid: ", addr_s(got_forbid_addr));
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$display(" granted: ", fshow(got_granted_op));
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$display(" want grants: ", fshow(tests[idx].want_grants));
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$display(" want forbid: ", addr_s(want_forbid_addr));
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$display(" want granted: ", fshow(want_granted_op));
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dynamicAssert(False, "wrong arbiter output");
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end
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@ -167,57 +156,60 @@ module mkTB(Empty);
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let strictTests = vec(
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// Simple grants
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testCase("All idle",
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vec(idle, idle, idle), noForbid,
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noGrant, noForbid),
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vec(idle, idle, idle), noConflict,
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noGrant, noConflict),
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testCase("Port 0 read",
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vec(read(1), idle, idle), noForbid,
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grant(0), noForbid),
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vec(read(1), idle, idle), noConflict,
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grant(0), read(1)),
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testCase("Port 0 write",
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vec(write(1), idle, idle), noForbid,
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grant(0), forbid(1)),
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vec(write(1), idle, idle), noConflict,
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grant(0), write(1)),
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testCase("Port 1 read",
|
||||
vec(idle, read(1), idle), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(idle, read(1), idle), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 1 write",
|
||||
vec(idle, write(1), idle), noForbid,
|
||||
grant(1), forbid(1)),
|
||||
vec(idle, write(1), idle), noConflict,
|
||||
grant(1), write(1)),
|
||||
testCase("Port 2 read",
|
||||
vec(idle, idle, read(1)), noForbid,
|
||||
grant(2), noForbid),
|
||||
vec(idle, idle, read(1)), noConflict,
|
||||
grant(2), read(1)),
|
||||
testCase("Port 2 write",
|
||||
vec(idle, idle, write(1)), noForbid,
|
||||
grant(2), forbid(1)),
|
||||
vec(idle, idle, write(1)), noConflict,
|
||||
grant(2), write(1)),
|
||||
|
||||
// Priorities
|
||||
testCase("Port 0+1",
|
||||
vec(read(1), read(2), idle), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), read(2), idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+2",
|
||||
vec(read(1), idle, read(2)), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), idle, read(2)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 1+2",
|
||||
vec(idle, read(1), read(2)), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(idle, read(1), read(2)), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 0+1+2",
|
||||
vec(read(1), read(2), read(3)), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), read(2), read(3)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2, overruled writes",
|
||||
vec(read(1), write(1), write(2)), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), write(1), write(2)), noConflict,
|
||||
grant(0), read(1)),
|
||||
|
||||
// Forbidden addrs
|
||||
testCase("Port 0 read denied",
|
||||
vec(read(1), read(2), idle), forbid(1),
|
||||
grant(1), noForbid),
|
||||
testCase("Port 0 write denied",
|
||||
vec(write(1), read(2), idle), forbid(1),
|
||||
grant(1), noForbid),
|
||||
testCase("Port 0 read-write denied",
|
||||
vec(read(1), read(2), idle), write(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 write-write denied",
|
||||
vec(write(1), read(2), idle), write(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 write-read denied",
|
||||
vec(write(1), read(2), idle), read(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 no addr match",
|
||||
vec(write(2), idle, idle), forbid(1),
|
||||
grant(0), forbid(2)),
|
||||
vec(write(2), idle, idle), write(1),
|
||||
grant(0), write(2)),
|
||||
testCase("Port 0 denied, no alternatives",
|
||||
vec(write(1), idle, idle), forbid(1),
|
||||
noGrant, noForbid)
|
||||
vec(write(1), idle, idle), write(1),
|
||||
noGrant, noConflict)
|
||||
);
|
||||
MemArbiter#(3, Addr) strict <- mkPriorityMemArbiter();
|
||||
let strictTB <- mkArbiterTB(strict, strictTests);
|
||||
|
|
@ -227,87 +219,87 @@ module mkTB(Empty);
|
|||
let rrTests = vec(
|
||||
// Simple grants
|
||||
testCase("All idle",
|
||||
vec(idle, idle, idle, idle), noForbid,
|
||||
noGrant, noForbid),
|
||||
vec(idle, idle, idle, idle), noConflict,
|
||||
noGrant, noConflict),
|
||||
testCase("Port 0 read",
|
||||
vec(read(1), idle, idle, idle), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), idle, idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0 write",
|
||||
vec(write(1), idle, idle, idle), noForbid,
|
||||
grant(0), forbid(1)),
|
||||
vec(write(1), idle, idle, idle), noConflict,
|
||||
grant(0), write(1)),
|
||||
testCase("Port 1 read",
|
||||
vec(idle, read(1), idle, idle), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(idle, read(1), idle, idle), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 1 write",
|
||||
vec(idle, write(1), idle, idle), noForbid,
|
||||
grant(1), forbid(1)),
|
||||
vec(idle, write(1), idle, idle), noConflict,
|
||||
grant(1), write(1)),
|
||||
testCase("Port 2 read",
|
||||
vec(idle, idle, read(1), idle), noForbid,
|
||||
grant(2), noForbid),
|
||||
vec(idle, idle, read(1), idle), noConflict,
|
||||
grant(2), read(1)),
|
||||
testCase("Port 2 write",
|
||||
vec(idle, idle, write(1), idle), noForbid,
|
||||
grant(2), forbid(1)),
|
||||
vec(idle, idle, write(1), idle), noConflict,
|
||||
grant(2), write(1)),
|
||||
testCase("Port 3 read",
|
||||
vec(idle, idle, idle, read(1)), noForbid,
|
||||
grant(3), noForbid),
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("Port 3 write",
|
||||
vec(idle, idle, idle, write(1)), noForbid,
|
||||
grant(3), forbid(1)),
|
||||
vec(idle, idle, idle, write(1)), noConflict,
|
||||
grant(3), write(1)),
|
||||
|
||||
// Priorities
|
||||
testCase("Port 3 to reset RR",
|
||||
vec(idle, idle, idle, read(1)), noForbid,
|
||||
grant(3), noForbid),
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("Port 0+1 #1",
|
||||
vec(read(1), read(2), idle, idle), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1 #2",
|
||||
vec(read(1), read(2), idle, idle), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0+1 #3",
|
||||
vec(read(1), read(2), idle, idle), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+2 #1",
|
||||
vec(read(1), idle, read(2), idle), noForbid,
|
||||
grant(2), noForbid),
|
||||
vec(read(1), idle, read(2), idle), noConflict,
|
||||
grant(2), read(2)),
|
||||
testCase("Port 0+2 #2",
|
||||
vec(read(1), idle, read(2), idle), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), idle, read(2), idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2+3 #1",
|
||||
vec(read(1), read(2), read(3), read(4)), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0+1+2+3 #2",
|
||||
vec(read(1), read(2), read(3), read(4)), noForbid,
|
||||
grant(2), noForbid),
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(2), read(3)),
|
||||
testCase("Port 0+1+2+3 #3",
|
||||
vec(read(1), read(2), read(3), read(4)), noForbid,
|
||||
grant(3), noForbid),
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(3), read(4)),
|
||||
testCase("Port 0+1+2+3 #4",
|
||||
vec(read(1), read(2), read(3), read(4)), noForbid,
|
||||
grant(0), noForbid),
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2+3 #5",
|
||||
vec(read(1), read(2), read(3), read(4)), noForbid,
|
||||
grant(1), noForbid),
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(1), read(2)),
|
||||
|
||||
// Forbidden addrs
|
||||
testCase("Port 3 to reset RR",
|
||||
vec(idle, idle, idle, read(1)), noForbid,
|
||||
grant(3), noForbid),
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("RR with denied writes #1",
|
||||
vec(read(1), write(2), read(3), read(4)), forbid(3),
|
||||
grant(0), noForbid),
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(0), read(1)),
|
||||
testCase("RR with denied writes #2",
|
||||
vec(read(1), write(2), read(3), read(4)), forbid(3),
|
||||
grant(1), forbid(2)),
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(1), write(2)),
|
||||
testCase("RR with denied writes #3",
|
||||
vec(read(1), write(2), read(3), read(4)), forbid(3),
|
||||
grant(3), noForbid),
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(3), read(4)),
|
||||
testCase("RR with denied writes #4",
|
||||
vec(read(1), write(2), read(3), read(4)), forbid(3),
|
||||
grant(0), noForbid),
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(0), read(1)),
|
||||
testCase("RR with denied writes #5",
|
||||
vec(read(1), write(2), read(3), read(4)), forbid(3),
|
||||
grant(1), forbid(2))
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(1), write(2))
|
||||
);
|
||||
MemArbiter#(4, Addr) rr <- mkRoundRobinMemArbiter();
|
||||
let rrTB <- mkArbiterTB(rr, rrTests);
|
||||
|
|
|
|||
Loading…
Reference in New Issue