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vram: move VRAM to VRAMCore, in prep for arbitrated VRAM

This commit is contained in:
David Anderson 2024-09-08 09:26:59 -07:00
parent 69b7ce7f9e
commit 2760bad965
2 changed files with 17 additions and 15 deletions
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6
experiments/vram/Top.bsv
View File

@ -1,12 +1,12 @@
package Top; package Top;
import VRAM::*; import VRAMCore::*;
import ECP5_RAM::*; import ECP5_RAM::*;
import TriState::*; import TriState::*;
(* synthesize *) (* synthesize *)
module mkTop(VRAM); module mkTop(VRAMCore);
let _ret <- mkVRAM(112); let _ret <- mkVRAMCore(112);
return _ret; return _ret;
endmodule endmodule

26
vram/VRAM.bsv → vram/VRAMCore.bsv
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@ -1,5 +1,6 @@
package VRAM; package VRAMCore;
import Connectable::*;
import GetPut::*; import GetPut::*;
import ClientServer::*; import ClientServer::*;
import DReg::*; import DReg::*;
@ -15,11 +16,12 @@ import ECP5_RAM::*;
export VRAMAddr; export VRAMAddr;
export VRAMData; export VRAMData;
export mkVRAM;
export VRAMRequest; export VRAMRequest;
export VRAMResponse; export VRAMResponse;
export VRAMClient;
export VRAMServer; export VRAMServer;
export VRAM; export VRAMCore;
export mkVRAMCore;
typedef Bit#(8) VRAMData; typedef Bit#(8) VRAMData;
@ -133,30 +135,30 @@ typedef struct {
typedef Server#(VRAMRequest, VRAMResponse) VRAMServer; typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
typedef Client#(VRAMRequest, VRAMResponse) VRAMClient; typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
interface VRAM; interface VRAMCore;
interface VRAMServer portA; interface VRAMServer portA;
interface VRAMServer portB; interface VRAMServer portB;
endinterface endinterface
// mkVRAM creates a dual port VRAM of the specified size, using ECP5 // mkVRAMCore creates a dual port VRAM of the specified size, using
// EBR memory primitives. The memory size must be a multiple of 4KiB, // ECP5 EBR memory primitives. The memory size must be a multiple of
// with a maximum of 128KiB. // 4KiB, with a maximum of 128KiB.
// //
// The returned VRAM servers implement flow control. As long as // The returned VRAMCore servers implement flow control. As long as
// responses are processed as soon as they're available, each port can // responses are processed as soon as they're available, each port can
// process one memory operation per cycle. // process one memory operation per cycle.
// //
// The VRAM does not prevent write-write or write-read conflicts // The VRAMCore does not prevent write-write or write-read conflicts
// between the ports. The outcome of a simultaneous write to the same // between the ports. The outcome of a simultaneous write to the same
// address is unspecified, as is the read output in a simultaneous // address is unspecified, as is the read output in a simultaneous
// read and write of the same address. The caller must use external // read and write of the same address. The caller must use external
// arbitration to avoid such accesses. // arbitration to avoid such accesses.
module mkVRAM(Integer num_kilobytes, VRAM ifc); module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
if (num_kilobytes > 128) if (num_kilobytes > 128)
error("maximum VRAM size is 128KiB"); error("maximum VRAMCore size is 128KiB");
let num_bytes = num_kilobytes*1024; let num_bytes = num_kilobytes*1024;
if (num_bytes % 4096 != 0) if (num_bytes % 4096 != 0)
error("VRAM must be a multiple of 4096b"); error("VRAMCore must be a multiple of 4096b");
let num_byterams = num_bytes/4096; let num_byterams = num_bytes/4096;
let num_arrays = ceil(fromInteger(num_byterams) / 8); let num_arrays = ceil(fromInteger(num_byterams) / 8);