vram: move VRAM to VRAMCore, in prep for arbitrated VRAM
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@ -1,12 +1,12 @@
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package Top;
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package Top;
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import VRAM::*;
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import VRAMCore::*;
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import ECP5_RAM::*;
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import ECP5_RAM::*;
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import TriState::*;
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import TriState::*;
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(* synthesize *)
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(* synthesize *)
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module mkTop(VRAM);
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module mkTop(VRAMCore);
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let _ret <- mkVRAM(112);
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let _ret <- mkVRAMCore(112);
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return _ret;
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return _ret;
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endmodule
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endmodule
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@ -1,5 +1,6 @@
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package VRAM;
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package VRAMCore;
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import Connectable::*;
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import GetPut::*;
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import GetPut::*;
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import ClientServer::*;
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import ClientServer::*;
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import DReg::*;
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import DReg::*;
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@ -15,11 +16,12 @@ import ECP5_RAM::*;
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export VRAMAddr;
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export VRAMAddr;
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export VRAMData;
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export VRAMData;
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export mkVRAM;
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export VRAMRequest;
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export VRAMRequest;
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export VRAMResponse;
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export VRAMResponse;
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export VRAMClient;
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export VRAMServer;
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export VRAMServer;
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export VRAM;
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export VRAMCore;
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export mkVRAMCore;
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typedef Bit#(8) VRAMData;
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typedef Bit#(8) VRAMData;
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@ -133,30 +135,30 @@ typedef struct {
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
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typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
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interface VRAM;
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interface VRAMCore;
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interface VRAMServer portA;
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interface VRAMServer portA;
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interface VRAMServer portB;
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interface VRAMServer portB;
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endinterface
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endinterface
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// mkVRAM creates a dual port VRAM of the specified size, using ECP5
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// mkVRAMCore creates a dual port VRAM of the specified size, using
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// EBR memory primitives. The memory size must be a multiple of 4KiB,
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// ECP5 EBR memory primitives. The memory size must be a multiple of
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// with a maximum of 128KiB.
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// 4KiB, with a maximum of 128KiB.
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//
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//
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// The returned VRAM servers implement flow control. As long as
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// The returned VRAMCore servers implement flow control. As long as
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// responses are processed as soon as they're available, each port can
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// responses are processed as soon as they're available, each port can
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// process one memory operation per cycle.
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// process one memory operation per cycle.
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//
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//
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// The VRAM does not prevent write-write or write-read conflicts
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// The VRAMCore does not prevent write-write or write-read conflicts
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// between the ports. The outcome of a simultaneous write to the same
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// between the ports. The outcome of a simultaneous write to the same
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// address is unspecified, as is the read output in a simultaneous
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// address is unspecified, as is the read output in a simultaneous
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// read and write of the same address. The caller must use external
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// read and write of the same address. The caller must use external
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// arbitration to avoid such accesses.
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// arbitration to avoid such accesses.
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module mkVRAM(Integer num_kilobytes, VRAM ifc);
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module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
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if (num_kilobytes > 128)
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if (num_kilobytes > 128)
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error("maximum VRAM size is 128KiB");
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error("maximum VRAMCore size is 128KiB");
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let num_bytes = num_kilobytes*1024;
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let num_bytes = num_kilobytes*1024;
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if (num_bytes % 4096 != 0)
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if (num_bytes % 4096 != 0)
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error("VRAM must be a multiple of 4096b");
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error("VRAMCore must be a multiple of 4096b");
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let num_byterams = num_bytes/4096;
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let num_byterams = num_bytes/4096;
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let num_arrays = ceil(fromInteger(num_byterams) / 8);
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let num_arrays = ceil(fromInteger(num_byterams) / 8);
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