lib/ClockOut: hack module to export a clock as an ordinary signal

Used to output a clock signal from an FPGA pin. The resultant output
signal is unclocked, so can be presented to any output at will.

lib/ClockOut.bsv

@@ -0,0 +1,16 @@
+package ClockOut;
+
+interface ClockOut;
+   method bit value();
+endinterface
+
+import "BVI" ClockOut =
+   module mkClockOut(ClockOut);
+      default_reset no_reset;
+      default_clock clk (CLK, (* unused *)GATE);
+
+      method CLK_BIT value() clocked_by(no_clock);
+
+      schedule value CF value;
+   endmodule
+endpackage

lib/ClockOut.v

@@ -0,0 +1,3 @@
+module ClockOut(input CLK, output CLK_BIT);
+  assign CLK_BIT = CLK;
+endmodule