Add some early testing harness for the sim DP16KD

2024-08-20 19:29:09 -07:00 · 2024-08-20 19:29:09 -07:00 · 119eeceaef
parent a4a10becbf
commit 119eeceaef
5 changed files with 179 additions and 65 deletions
--- a/sim/.gtkwaverc
+++ b/sim/.gtkwaverc
@ -0,0 +1 @@
+splash_disable on
--- a/sim/DP16KD.v
+++ b/sim/DP16KD.v
@ -29,39 +29,45 @@ module DP16KD__INTERNAL#(

  wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}};

+  wire addr_collision = ADA == ADB;
+  wire write_collision = addr_collision && WEA && WEB;
+  wire read_collision = addr_collision && (WEA || WEB);
+
  if (RESETMODE == "SYNC") begin : sync_ram
-    always @(posedge CLKA) begin
+    always @(posedge CLKA, posedge CLKB) begin
+      if (CLKA) begin
        if (RSTA)
          DOA <= {DATA_WIDTH {1'b0}};
        else if (CEA) begin
          if (WEA) begin
-          ram[ADA] <= DIA;
+            ram[ADA] <= write_collision ? undef : DIA;
            case (WRITEMODE_A)
              "NORMAL": DOA <= undef;
              "WRITETHROUGH": DOA <= DIA;
-            "READBEFOREWRITE": DOA <= ram[ADA];
+              "READBEFOREWRITE": DOA <= read_collision ? undef : ram[ADA];
            endcase
          end
          else
-          DOA <= ram[ADA];
-      end
+            DOA <= read_collision ? undef : ram[ADA];
        end
+      end // if (CLKA)

-    always @(posedge CLKB) begin
+      if (CLKB) begin
        if (RSTB)
          DOB <= {DATA_WIDTH {1'b0}};
        else if (CEB) begin
          if (WEB) begin
-          ram[ADB] <= DIB;
+            ram[ADB] <= write_collision ? undef : DIB;
            case (WRITEMODE_B)
              "NORMAL": DOB <= undef;
              "WRITETHROUGH": DOB <= DIB;
-            "READBEFOREWRITE": DOB <= ram[ADB];
+              "READBEFOREWRITE": DOB <= read_collision ? undef : ram[ADB];
            endcase
          end
          else
-          DOB <= ram[ADB];
+            DOB <= read_collision ? undef : ram[ADB];
        end
+      end // if (CLKB)
    end
  end // if (RESETMODE == "SYNC")
  else begin : async_ram
--- a/sim/run.sh
+++ b/sim/run.sh
@ -0,0 +1,38 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+run() {
+    base="$1"
+    variant="$2"
+    shift 2
+
+    mkdir -p gen
+    iverilog -Wall -o test.out "$@" "tb/tb_DP16KD_${base}.v" DP16KD.v
+    ./test.out
+    rm -f test.out
+    dir=$(readlink -f `dirname $0`)
+    vcdfile="${variant}.vcd"
+    mv tb.vcd "${dir}/gen/$vcdfile"
+    gtkwfile="${variant}.gtkw"
+    cp tb_cfg.gtkw "${dir}/gen/$gtkwfile"
+    perl -p -e "s#WORKING_DIR#$dir#g;" -e "s#VCDFILE#${vcdfile}#g;" -e "s#GTKWFILE#${gtkwfile}#g;" <tb_cfg.gtkw >"${dir}/gen/$gtkwfile"
+}
+
+rm -rf gen
+
+run sync_same_width 18b_sync_same_width \
+    -P tb.DATA_WIDTH_A=18 -P tb.DATA_WIDTH_B=18 \
+    -P tb.ADDR_WIDTH_A=10 -P tb.ADDR_WIDTH_B=10
+run sync_same_width 9b_sync_same_width \
+    -P tb.DATA_WIDTH_A=9 -P tb.DATA_WIDTH_B=9 \
+    -P tb.ADDR_WIDTH_A=11 -P tb.ADDR_WIDTH_B=11
+run sync_same_width 4b_sync_same_width \
+    -P tb.DATA_WIDTH_A=4 -P tb.DATA_WIDTH_B=4 \
+    -P tb.ADDR_WIDTH_A=12 -P tb.ADDR_WIDTH_B=12
+run sync_same_width 2b_sync_same_width \
+    -P tb.DATA_WIDTH_A=2 -P tb.DATA_WIDTH_B=2 \
+    -P tb.ADDR_WIDTH_A=13 -P tb.ADDR_WIDTH_B=13
+run sync_same_width 1b_sync_same_width \
+    -P tb.DATA_WIDTH_A=1 -P tb.DATA_WIDTH_B=1 \
+    -P tb.ADDR_WIDTH_A=14 -P tb.ADDR_WIDTH_B=14
--- a/sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
+++ b/sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
@ -1,43 +1,38 @@
-module tb_DP16KD_18b_sync_nowriteout_unregistered#(
-  parameter WRITEMODE_A="NORMAL",
-  parameter WRITEMODE_B="NORMAL",
-  parameter REGMODE_A="NOREG",
-  parameter REGMODE_B="NOREG",
-  parameter RESETMODE="SYNC",
-  parameter ASYNC_RESET_RELEASE="SYNC",
+module tb#(
  parameter DATA_WIDTH_A=18,
  parameter DATA_WIDTH_B=18,
  parameter ADDR_WIDTH_A=10,
-  parameter ADDR_WIDTH_B=10,
-  parameter ADDR_MAX_A=1023,
-  parameter ADDR_MAX_B=1023,
-  parameter DATA_MAX_A=18'h3FFFF,
-  parameter DATA_MAX_B=18'h3FFFF
+  parameter ADDR_WIDTH_B=10
 );
+  localparam ADDR_MAX_A = 2**ADDR_WIDTH_A - 1;
+  localparam ADDR_MAX_B = 2**ADDR_WIDTH_B - 1;
+  localparam DATA_MAX_A = 2**DATA_WIDTH_A - 1;
+  localparam DATA_MAX_B = 2**DATA_WIDTH_B - 1;
+
  reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
  reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
  reg [2:0] CSA=0, CSB=0;
-  reg [ADDR_WIDTH_A-1:0] ADA;
-  reg [ADDR_WIDTH_B-1:0] ADB;
-  reg [DATA_WIDTH_A-1:0] DIA;
-  reg [DATA_WIDTH_B-1:0] DIB;
-  wire [DATA_WIDTH_A-1:0] DOA;
-  wire [DATA_WIDTH_B-1:0] DOB;
-  reg [DATA_WIDTH_A-1:0] WANTA;
-  reg [DATA_WIDTH_B-1:0] WANTB;
+  reg [13:0] ADA;
+  reg [13:0] ADB;
+  reg [17:0] DIA;
+  reg [17:0] DIB;
+  wire [17:0] DOA;
+  wire [17:0] DOB;
+  reg [17:0] WANTA;
+  reg [17:0] WANTB;
  wire BADA = DOA !== WANTA;
  wire BADB = DOB !== WANTB;
  reg [239:0] TESTNAME;

-  wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
-  wire [DATA_WIDTH_B-1:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
+  wire [17:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
+  wire [17:0] UNDEFB = {DATA_WIDTH_B{1'bx}};

-  DP16KD#(.WRITEMODE_A(WRITEMODE_A),
-          .WRITEMODE_B(WRITEMODE_B),
-          .REGMODE_A(REGMODE_A),
-          .REGMODE_B(REGMODE_B),
-          .RESETMODE(RESETMODE),
-          .ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
+  DP16KD#(.WRITEMODE_A("NORMAL"),
+          .WRITEMODE_B("NORMAL"),
+          .REGMODE_A("NOREG"),
+          .REGMODE_B("NOREG"),
+          .RESETMODE("SYNC"),
+          .ASYNC_RESET_RELEASE("SYNC"),
          .DATA_WIDTH_A(DATA_WIDTH_A),
          .DATA_WIDTH_B(DATA_WIDTH_B)
          ) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
@ -59,9 +54,10 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
  end

  initial begin
-    $dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered");
-    $dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered);
+    $dumpfile("tb");
+    $dumpvars(0, tb);
    #10
+
    // Write to lowest and highest addrs, read back from the other port.
    TESTNAME="SIMPLE WRITE/READ 1";
    ADA=0;          DIA=1;          CEA=1; WEA=1; // Write min addr
@ -80,8 +76,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(

    // Swap values around, read back from other port.
    TESTNAME="SIMPLE WRITE/READ 2";
-    ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A; CEA=1; WEA=1; // Write max addr
-    ADB=1;            DIB=1;          CEB=1; WEB=1; // Write min addr
+    ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A-1; CEA=1; WEA=1; // Write max addr
+    ADB=1;            DIB=2;            CEB=1; WEB=1; // Write min addr
    #5
    WANTA=UNDEFA;
    WANTB=UNDEFB;
@ -90,8 +86,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
    ADA=1;            DIA=0; CEA=1; WEA=0; // Read min addr
    ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
    #5
-    WANTA=1;
-    WANTB=DATA_MAX_B;
+    WANTA=2;
+    WANTB=DATA_MAX_B-1;
    #5

    // No change when reading and not enabled
--- a/sim/tb_cfg.gtkw
+++ b/sim/tb_cfg.gtkw
@ -0,0 +1,73 @@
+[*]
+[*] GTKWave Analyzer v3.3.120 (w)1999-2024 BSI
+[*] Sat Aug 31 03:16:28 2024
+[*]
+[dumpfile] "WORKING_DIR/VCDFILE"
+[dumpfile_mtime] "Sat Aug 31 03:12:41 2024"
+[dumpfile_size] 28485
+[savefile] "WORKING_DIR/GTKWFILE"
+[timestart] 0
+[size] 2556 660
+[pos] -1 -1
+*-4.261485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.uut.
+[sst_width] 282
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 164
+@820
+[color] 5
+tb.TESTNAME[239:0]
+[color] 5
+tb.WRITEMODE_A
+@821
+[color] 5
+tb.WRITEMODE_B
+@200
+-
+@28
+tb.RSTA
+tb.CEA
+tb.CSA[2:0]
+@22
+tb.ADA[13:0]
+tb.DIA[17:0]
+@28
+[color] 3
+tb.WEA
+[color] 7
+tb.CLKA
+@22
+tb.DOA[17:0]
+[color] 2
+tb.WANTA[17:0]
+@28
+[color] 1
+tb.BADA
+@200
+-
+-
+@28
+tb.RSTB
+@29
+tb.CEB
+@28
+tb.CSB[2:0]
+@22
+tb.ADB[13:0]
+tb.DIB[17:0]
+@28
+[color] 3
+tb.WEB
+[color] 7
+tb.CLKB
+@22
+tb.DOB[17:0]
+[color] 2
+tb.WANTB[17:0]
+@28
+[color] 1
+tb.BADB
+[pattern_trace] 1
+[pattern_trace] 0