Add some early testing harness for the sim DP16KD

This commit is contained in:
David Anderson 2024-08-20 19:29:09 -07:00
parent a4a10becbf
commit 119eeceaef
5 changed files with 179 additions and 65 deletions

1
sim/.gtkwaverc Normal file
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@ -0,0 +1 @@
splash_disable on

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@ -29,39 +29,45 @@ module DP16KD__INTERNAL#(
wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}}; wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}};
if (RESETMODE == "SYNC") begin : sync_ram wire addr_collision = ADA == ADB;
always @(posedge CLKA) begin wire write_collision = addr_collision && WEA && WEB;
if (RSTA) wire read_collision = addr_collision && (WEA || WEB);
DOA <= {DATA_WIDTH {1'b0}};
else if (CEA) begin
if (WEA) begin
ram[ADA] <= DIA;
case (WRITEMODE_A)
"NORMAL": DOA <= undef;
"WRITETHROUGH": DOA <= DIA;
"READBEFOREWRITE": DOA <= ram[ADA];
endcase
end
else
DOA <= ram[ADA];
end
end
always @(posedge CLKB) begin if (RESETMODE == "SYNC") begin : sync_ram
if (RSTB) always @(posedge CLKA, posedge CLKB) begin
DOB <= {DATA_WIDTH {1'b0}}; if (CLKA) begin
else if (CEB) begin if (RSTA)
if (WEB) begin DOA <= {DATA_WIDTH {1'b0}};
ram[ADB] <= DIB; else if (CEA) begin
case (WRITEMODE_B) if (WEA) begin
"NORMAL": DOB <= undef; ram[ADA] <= write_collision ? undef : DIA;
"WRITETHROUGH": DOB <= DIB; case (WRITEMODE_A)
"READBEFOREWRITE": DOB <= ram[ADB]; "NORMAL": DOA <= undef;
endcase "WRITETHROUGH": DOA <= DIA;
"READBEFOREWRITE": DOA <= read_collision ? undef : ram[ADA];
endcase
end
else
DOA <= read_collision ? undef : ram[ADA];
end end
else end // if (CLKA)
DOB <= ram[ADB];
end if (CLKB) begin
if (RSTB)
DOB <= {DATA_WIDTH {1'b0}};
else if (CEB) begin
if (WEB) begin
ram[ADB] <= write_collision ? undef : DIB;
case (WRITEMODE_B)
"NORMAL": DOB <= undef;
"WRITETHROUGH": DOB <= DIB;
"READBEFOREWRITE": DOB <= read_collision ? undef : ram[ADB];
endcase
end
else
DOB <= read_collision ? undef : ram[ADB];
end
end // if (CLKB)
end end
end // if (RESETMODE == "SYNC") end // if (RESETMODE == "SYNC")
else begin : async_ram else begin : async_ram

38
sim/run.sh Executable file
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#!/usr/bin/env bash
set -euo pipefail
run() {
base="$1"
variant="$2"
shift 2
mkdir -p gen
iverilog -Wall -o test.out "$@" "tb/tb_DP16KD_${base}.v" DP16KD.v
./test.out
rm -f test.out
dir=$(readlink -f `dirname $0`)
vcdfile="${variant}.vcd"
mv tb.vcd "${dir}/gen/$vcdfile"
gtkwfile="${variant}.gtkw"
cp tb_cfg.gtkw "${dir}/gen/$gtkwfile"
perl -p -e "s#WORKING_DIR#$dir#g;" -e "s#VCDFILE#${vcdfile}#g;" -e "s#GTKWFILE#${gtkwfile}#g;" <tb_cfg.gtkw >"${dir}/gen/$gtkwfile"
}
rm -rf gen
run sync_same_width 18b_sync_same_width \
-P tb.DATA_WIDTH_A=18 -P tb.DATA_WIDTH_B=18 \
-P tb.ADDR_WIDTH_A=10 -P tb.ADDR_WIDTH_B=10
run sync_same_width 9b_sync_same_width \
-P tb.DATA_WIDTH_A=9 -P tb.DATA_WIDTH_B=9 \
-P tb.ADDR_WIDTH_A=11 -P tb.ADDR_WIDTH_B=11
run sync_same_width 4b_sync_same_width \
-P tb.DATA_WIDTH_A=4 -P tb.DATA_WIDTH_B=4 \
-P tb.ADDR_WIDTH_A=12 -P tb.ADDR_WIDTH_B=12
run sync_same_width 2b_sync_same_width \
-P tb.DATA_WIDTH_A=2 -P tb.DATA_WIDTH_B=2 \
-P tb.ADDR_WIDTH_A=13 -P tb.ADDR_WIDTH_B=13
run sync_same_width 1b_sync_same_width \
-P tb.DATA_WIDTH_A=1 -P tb.DATA_WIDTH_B=1 \
-P tb.ADDR_WIDTH_A=14 -P tb.ADDR_WIDTH_B=14

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@ -1,43 +1,38 @@
module tb_DP16KD_18b_sync_nowriteout_unregistered#( module tb#(
parameter WRITEMODE_A="NORMAL",
parameter WRITEMODE_B="NORMAL",
parameter REGMODE_A="NOREG",
parameter REGMODE_B="NOREG",
parameter RESETMODE="SYNC",
parameter ASYNC_RESET_RELEASE="SYNC",
parameter DATA_WIDTH_A=18, parameter DATA_WIDTH_A=18,
parameter DATA_WIDTH_B=18, parameter DATA_WIDTH_B=18,
parameter ADDR_WIDTH_A=10, parameter ADDR_WIDTH_A=10,
parameter ADDR_WIDTH_B=10, parameter ADDR_WIDTH_B=10
parameter ADDR_MAX_A=1023,
parameter ADDR_MAX_B=1023,
parameter DATA_MAX_A=18'h3FFFF,
parameter DATA_MAX_B=18'h3FFFF
); );
localparam ADDR_MAX_A = 2**ADDR_WIDTH_A - 1;
localparam ADDR_MAX_B = 2**ADDR_WIDTH_B - 1;
localparam DATA_MAX_A = 2**DATA_WIDTH_A - 1;
localparam DATA_MAX_B = 2**DATA_WIDTH_B - 1;
reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0; reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0; reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
reg [2:0] CSA=0, CSB=0; reg [2:0] CSA=0, CSB=0;
reg [ADDR_WIDTH_A-1:0] ADA; reg [13:0] ADA;
reg [ADDR_WIDTH_B-1:0] ADB; reg [13:0] ADB;
reg [DATA_WIDTH_A-1:0] DIA; reg [17:0] DIA;
reg [DATA_WIDTH_B-1:0] DIB; reg [17:0] DIB;
wire [DATA_WIDTH_A-1:0] DOA; wire [17:0] DOA;
wire [DATA_WIDTH_B-1:0] DOB; wire [17:0] DOB;
reg [DATA_WIDTH_A-1:0] WANTA; reg [17:0] WANTA;
reg [DATA_WIDTH_B-1:0] WANTB; reg [17:0] WANTB;
wire BADA = DOA !== WANTA; wire BADA = DOA !== WANTA;
wire BADB = DOB !== WANTB; wire BADB = DOB !== WANTB;
reg [239:0] TESTNAME; reg [239:0] TESTNAME;
wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}}; wire [17:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
wire [DATA_WIDTH_B-1:0] UNDEFB = {DATA_WIDTH_B{1'bx}}; wire [17:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
DP16KD#(.WRITEMODE_A(WRITEMODE_A), DP16KD#(.WRITEMODE_A("NORMAL"),
.WRITEMODE_B(WRITEMODE_B), .WRITEMODE_B("NORMAL"),
.REGMODE_A(REGMODE_A), .REGMODE_A("NOREG"),
.REGMODE_B(REGMODE_B), .REGMODE_B("NOREG"),
.RESETMODE(RESETMODE), .RESETMODE("SYNC"),
.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE), .ASYNC_RESET_RELEASE("SYNC"),
.DATA_WIDTH_A(DATA_WIDTH_A), .DATA_WIDTH_A(DATA_WIDTH_A),
.DATA_WIDTH_B(DATA_WIDTH_B) .DATA_WIDTH_B(DATA_WIDTH_B)
) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA), ) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
@ -59,9 +54,10 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
end end
initial begin initial begin
$dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered"); $dumpfile("tb");
$dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered); $dumpvars(0, tb);
#10 #10
// Write to lowest and highest addrs, read back from the other port. // Write to lowest and highest addrs, read back from the other port.
TESTNAME="SIMPLE WRITE/READ 1"; TESTNAME="SIMPLE WRITE/READ 1";
ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr
@ -80,8 +76,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
// Swap values around, read back from other port. // Swap values around, read back from other port.
TESTNAME="SIMPLE WRITE/READ 2"; TESTNAME="SIMPLE WRITE/READ 2";
ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A; CEA=1; WEA=1; // Write max addr ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A-1; CEA=1; WEA=1; // Write max addr
ADB=1; DIB=1; CEB=1; WEB=1; // Write min addr ADB=1; DIB=2; CEB=1; WEB=1; // Write min addr
#5 #5
WANTA=UNDEFA; WANTA=UNDEFA;
WANTB=UNDEFB; WANTB=UNDEFB;
@ -90,8 +86,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr
ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
#5 #5
WANTA=1; WANTA=2;
WANTB=DATA_MAX_B; WANTB=DATA_MAX_B-1;
#5 #5
// No change when reading and not enabled // No change when reading and not enabled

73
sim/tb_cfg.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.3.120 (w)1999-2024 BSI
[*] Sat Aug 31 03:16:28 2024
[*]
[dumpfile] "WORKING_DIR/VCDFILE"
[dumpfile_mtime] "Sat Aug 31 03:12:41 2024"
[dumpfile_size] 28485
[savefile] "WORKING_DIR/GTKWFILE"
[timestart] 0
[size] 2556 660
[pos] -1 -1
*-4.261485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[treeopen] tb.uut.
[sst_width] 282
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 164
@820
[color] 5
tb.TESTNAME[239:0]
[color] 5
tb.WRITEMODE_A
@821
[color] 5
tb.WRITEMODE_B
@200
-
@28
tb.RSTA
tb.CEA
tb.CSA[2:0]
@22
tb.ADA[13:0]
tb.DIA[17:0]
@28
[color] 3
tb.WEA
[color] 7
tb.CLKA
@22
tb.DOA[17:0]
[color] 2
tb.WANTA[17:0]
@28
[color] 1
tb.BADA
@200
-
-
@28
tb.RSTB
@29
tb.CEB
@28
tb.CSB[2:0]
@22
tb.ADB[13:0]
tb.DIB[17:0]
@28
[color] 3
tb.WEB
[color] 7
tb.CLKB
@22
tb.DOB[17:0]
[color] 2
tb.WANTB[17:0]
@28
[color] 1
tb.BADB
[pattern_trace] 1
[pattern_trace] 0