Add some early testing harness for the sim DP16KD
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a4a10becbf
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splash_disable on
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24
sim/DP16KD.v
24
sim/DP16KD.v
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@ -29,39 +29,45 @@ module DP16KD__INTERNAL#(
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wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}};
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wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}};
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wire addr_collision = ADA == ADB;
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wire write_collision = addr_collision && WEA && WEB;
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wire read_collision = addr_collision && (WEA || WEB);
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if (RESETMODE == "SYNC") begin : sync_ram
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if (RESETMODE == "SYNC") begin : sync_ram
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always @(posedge CLKA) begin
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always @(posedge CLKA, posedge CLKB) begin
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if (CLKA) begin
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if (RSTA)
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if (RSTA)
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DOA <= {DATA_WIDTH {1'b0}};
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DOA <= {DATA_WIDTH {1'b0}};
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else if (CEA) begin
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else if (CEA) begin
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if (WEA) begin
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if (WEA) begin
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ram[ADA] <= DIA;
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ram[ADA] <= write_collision ? undef : DIA;
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case (WRITEMODE_A)
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case (WRITEMODE_A)
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"NORMAL": DOA <= undef;
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"NORMAL": DOA <= undef;
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"WRITETHROUGH": DOA <= DIA;
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"WRITETHROUGH": DOA <= DIA;
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"READBEFOREWRITE": DOA <= ram[ADA];
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"READBEFOREWRITE": DOA <= read_collision ? undef : ram[ADA];
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endcase
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endcase
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end
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end
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else
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else
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DOA <= ram[ADA];
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DOA <= read_collision ? undef : ram[ADA];
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end
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end
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end
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end // if (CLKA)
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always @(posedge CLKB) begin
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if (CLKB) begin
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if (RSTB)
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if (RSTB)
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DOB <= {DATA_WIDTH {1'b0}};
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DOB <= {DATA_WIDTH {1'b0}};
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else if (CEB) begin
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else if (CEB) begin
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if (WEB) begin
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if (WEB) begin
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ram[ADB] <= DIB;
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ram[ADB] <= write_collision ? undef : DIB;
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case (WRITEMODE_B)
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case (WRITEMODE_B)
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"NORMAL": DOB <= undef;
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"NORMAL": DOB <= undef;
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"WRITETHROUGH": DOB <= DIB;
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"WRITETHROUGH": DOB <= DIB;
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"READBEFOREWRITE": DOB <= ram[ADB];
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"READBEFOREWRITE": DOB <= read_collision ? undef : ram[ADB];
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endcase
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endcase
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end
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end
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else
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else
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DOB <= ram[ADB];
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DOB <= read_collision ? undef : ram[ADB];
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end
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end
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end // if (CLKB)
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end
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end
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end // if (RESETMODE == "SYNC")
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end // if (RESETMODE == "SYNC")
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else begin : async_ram
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else begin : async_ram
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@ -0,0 +1,38 @@
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#!/usr/bin/env bash
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set -euo pipefail
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run() {
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base="$1"
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variant="$2"
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shift 2
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mkdir -p gen
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iverilog -Wall -o test.out "$@" "tb/tb_DP16KD_${base}.v" DP16KD.v
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./test.out
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rm -f test.out
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dir=$(readlink -f `dirname $0`)
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vcdfile="${variant}.vcd"
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mv tb.vcd "${dir}/gen/$vcdfile"
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gtkwfile="${variant}.gtkw"
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cp tb_cfg.gtkw "${dir}/gen/$gtkwfile"
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perl -p -e "s#WORKING_DIR#$dir#g;" -e "s#VCDFILE#${vcdfile}#g;" -e "s#GTKWFILE#${gtkwfile}#g;" <tb_cfg.gtkw >"${dir}/gen/$gtkwfile"
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}
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rm -rf gen
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run sync_same_width 18b_sync_same_width \
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-P tb.DATA_WIDTH_A=18 -P tb.DATA_WIDTH_B=18 \
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-P tb.ADDR_WIDTH_A=10 -P tb.ADDR_WIDTH_B=10
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run sync_same_width 9b_sync_same_width \
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-P tb.DATA_WIDTH_A=9 -P tb.DATA_WIDTH_B=9 \
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-P tb.ADDR_WIDTH_A=11 -P tb.ADDR_WIDTH_B=11
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run sync_same_width 4b_sync_same_width \
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-P tb.DATA_WIDTH_A=4 -P tb.DATA_WIDTH_B=4 \
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-P tb.ADDR_WIDTH_A=12 -P tb.ADDR_WIDTH_B=12
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run sync_same_width 2b_sync_same_width \
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-P tb.DATA_WIDTH_A=2 -P tb.DATA_WIDTH_B=2 \
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-P tb.ADDR_WIDTH_A=13 -P tb.ADDR_WIDTH_B=13
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run sync_same_width 1b_sync_same_width \
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-P tb.DATA_WIDTH_A=1 -P tb.DATA_WIDTH_B=1 \
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-P tb.ADDR_WIDTH_A=14 -P tb.ADDR_WIDTH_B=14
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@ -1,43 +1,38 @@
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module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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module tb#(
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parameter WRITEMODE_A="NORMAL",
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parameter WRITEMODE_B="NORMAL",
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parameter REGMODE_A="NOREG",
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parameter REGMODE_B="NOREG",
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parameter RESETMODE="SYNC",
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parameter ASYNC_RESET_RELEASE="SYNC",
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parameter DATA_WIDTH_A=18,
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parameter DATA_WIDTH_A=18,
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parameter DATA_WIDTH_B=18,
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parameter DATA_WIDTH_B=18,
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parameter ADDR_WIDTH_A=10,
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parameter ADDR_WIDTH_A=10,
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parameter ADDR_WIDTH_B=10,
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parameter ADDR_WIDTH_B=10
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parameter ADDR_MAX_A=1023,
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parameter ADDR_MAX_B=1023,
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parameter DATA_MAX_A=18'h3FFFF,
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parameter DATA_MAX_B=18'h3FFFF
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);
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);
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localparam ADDR_MAX_A = 2**ADDR_WIDTH_A - 1;
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localparam ADDR_MAX_B = 2**ADDR_WIDTH_B - 1;
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localparam DATA_MAX_A = 2**DATA_WIDTH_A - 1;
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localparam DATA_MAX_B = 2**DATA_WIDTH_B - 1;
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reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
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reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
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reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
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reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
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reg [2:0] CSA=0, CSB=0;
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reg [2:0] CSA=0, CSB=0;
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reg [ADDR_WIDTH_A-1:0] ADA;
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reg [13:0] ADA;
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reg [ADDR_WIDTH_B-1:0] ADB;
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reg [13:0] ADB;
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reg [DATA_WIDTH_A-1:0] DIA;
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reg [17:0] DIA;
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reg [DATA_WIDTH_B-1:0] DIB;
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reg [17:0] DIB;
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wire [DATA_WIDTH_A-1:0] DOA;
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wire [17:0] DOA;
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wire [DATA_WIDTH_B-1:0] DOB;
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wire [17:0] DOB;
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reg [DATA_WIDTH_A-1:0] WANTA;
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reg [17:0] WANTA;
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reg [DATA_WIDTH_B-1:0] WANTB;
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reg [17:0] WANTB;
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wire BADA = DOA !== WANTA;
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wire BADA = DOA !== WANTA;
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wire BADB = DOB !== WANTB;
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wire BADB = DOB !== WANTB;
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reg [239:0] TESTNAME;
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reg [239:0] TESTNAME;
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wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
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wire [17:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
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wire [DATA_WIDTH_B-1:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
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wire [17:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
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DP16KD#(.WRITEMODE_A(WRITEMODE_A),
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DP16KD#(.WRITEMODE_A("NORMAL"),
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.WRITEMODE_B(WRITEMODE_B),
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.WRITEMODE_B("NORMAL"),
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.REGMODE_A(REGMODE_A),
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.REGMODE_A("NOREG"),
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.REGMODE_B(REGMODE_B),
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.REGMODE_B("NOREG"),
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.RESETMODE(RESETMODE),
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.RESETMODE("SYNC"),
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.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
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.ASYNC_RESET_RELEASE("SYNC"),
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.DATA_WIDTH_A(DATA_WIDTH_A),
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.DATA_WIDTH_A(DATA_WIDTH_A),
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.DATA_WIDTH_B(DATA_WIDTH_B)
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.DATA_WIDTH_B(DATA_WIDTH_B)
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) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
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) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
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@ -59,9 +54,10 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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end
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end
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initial begin
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initial begin
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$dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered");
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$dumpfile("tb");
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$dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered);
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$dumpvars(0, tb);
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#10
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#10
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// Write to lowest and highest addrs, read back from the other port.
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// Write to lowest and highest addrs, read back from the other port.
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TESTNAME="SIMPLE WRITE/READ 1";
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TESTNAME="SIMPLE WRITE/READ 1";
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ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr
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ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr
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@ -80,8 +76,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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// Swap values around, read back from other port.
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// Swap values around, read back from other port.
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TESTNAME="SIMPLE WRITE/READ 2";
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TESTNAME="SIMPLE WRITE/READ 2";
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ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A; CEA=1; WEA=1; // Write max addr
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ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A-1; CEA=1; WEA=1; // Write max addr
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ADB=1; DIB=1; CEB=1; WEB=1; // Write min addr
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ADB=1; DIB=2; CEB=1; WEB=1; // Write min addr
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#5
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#5
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WANTA=UNDEFA;
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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WANTB=UNDEFB;
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@ -90,8 +86,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr
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ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr
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ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
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ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
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#5
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#5
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WANTA=1;
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WANTA=2;
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WANTB=DATA_MAX_B;
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WANTB=DATA_MAX_B-1;
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#5
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#5
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// No change when reading and not enabled
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// No change when reading and not enabled
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@ -0,0 +1,73 @@
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[*]
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[*] GTKWave Analyzer v3.3.120 (w)1999-2024 BSI
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[*] Sat Aug 31 03:16:28 2024
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[*]
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[dumpfile] "WORKING_DIR/VCDFILE"
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[dumpfile_mtime] "Sat Aug 31 03:12:41 2024"
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[dumpfile_size] 28485
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[savefile] "WORKING_DIR/GTKWFILE"
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[timestart] 0
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[size] 2556 660
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[pos] -1 -1
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*-4.261485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[treeopen] tb.uut.
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[sst_width] 282
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[signals_width] 150
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[sst_expanded] 1
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[sst_vpaned_height] 164
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@820
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[color] 5
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tb.TESTNAME[239:0]
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[color] 5
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tb.WRITEMODE_A
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@821
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[color] 5
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tb.WRITEMODE_B
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@200
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-
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@28
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tb.RSTA
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tb.CEA
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tb.CSA[2:0]
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@22
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tb.ADA[13:0]
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tb.DIA[17:0]
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@28
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[color] 3
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tb.WEA
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[color] 7
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tb.CLKA
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@22
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tb.DOA[17:0]
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[color] 2
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tb.WANTA[17:0]
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@28
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[color] 1
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tb.BADA
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@200
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-
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-
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@28
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tb.RSTB
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@29
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tb.CEB
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@28
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tb.CSB[2:0]
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@22
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tb.ADB[13:0]
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tb.DIB[17:0]
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@28
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[color] 3
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tb.WEB
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[color] 7
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tb.CLKB
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@22
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tb.DOB[17:0]
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[color] 2
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tb.WANTB[17:0]
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@28
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[color] 1
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tb.BADB
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[pattern_trace] 1
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[pattern_trace] 0
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