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sentinel65x/PLL: update PLL settings, fix generator

This commit is contained in:
David Anderson 2024-09-06 21:08:51 -07:00
parent d960eee973
commit 0005ad6fe5
3 changed files with 5 additions and 5 deletions
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2
sentinel65x/PLL.bsv
View File

@ -1,6 +1,6 @@
package PLL;
// Frequencies: FPGA 100MHz, CPU 10MHz, VGA 25MHz
// Frequencies: FPGA 100MHz, CPU 8MHz, VGA 25MHz
//
// To regenerate, see 'inv genclk -h'

6
sentinel65x/PLL.v
View File

@ -6,13 +6,13 @@ module PLL
(
input CLK_REF, // 25 MHz, 0 deg
output CLK_MAIN, // 100 MHz, 0 deg
output CLK_CPU, // 10 MHz, 0 deg
output CLK_CPU, // 8 MHz, 0 deg
output CLK_VGA, // 25 MHz, 0 deg
output locked
);
(* FREQUENCY_PIN_CLKI="25" *)
(* FREQUENCY_PIN_CLKOP="100" *)
(* FREQUENCY_PIN_CLKOS="10" *)
(* FREQUENCY_PIN_CLKOS="8" *)
(* FREQUENCY_PIN_CLKOS2="25" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
@ -30,7 +30,7 @@ EHXPLLL #(
.CLKOP_CPHASE(2),
.CLKOP_FPHASE(0),
.CLKOS_ENABLE("ENABLED"),
.CLKOS_DIV(60),
.CLKOS_DIV(75),
.CLKOS_CPHASE(2),
.CLKOS_FPHASE(0),
.CLKOS2_ENABLE("ENABLED"),

2
tasks.py
View File

@ -205,7 +205,7 @@ def clean(c):
@task
def genclk(c, in_mhz=25, main_mhz=100, cpu_mhz=10, vga_mhz=25):
out = Path("gary/PLL.v")
out = Path("sentinel65x/PLL.v")
c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
bsv_out = out.with_suffix(".bsv")
with open(bsv_out) as f: