dave
/
gary
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
gary/lib/DelayLine_Test.bsv

91 lines
2.9 KiB
Plaintext
Raw Normal View History

lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
package DelayLine_Test;
import Assert::*;
import StmtFSM::*;
import Testing::*;
import Printf::*;
import List::*;
import DelayLine::*;
module mkTB();
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
let testflags <- mkTestFlags();
lib: add more documentation
2024-08-14 05:53:47 +02:00
let cycles <- mkCycleCounter();
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
seq
action
delay <= 42;
lib: add more documentation
2024-08-14 05:53:47 +02:00
cycles.reset();
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
endaction
repeat (wantDelay-1)
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
action
if (delay.ready) begin
$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish;
end
endaction
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
// Check the value coming off the delay line and the timing
// separately, since the delay line read can be blocked by
// implicit conditions.
par
dynamicAssert(delay == 42, "delay output was wrong value");
action
dynamicAssert(delay.ready == True, "delay line not ready when expected");
lib: add more documentation
2024-08-14 05:53:47 +02:00
if (cycles != wantDelay) begin
$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
$finish;
end
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
endaction
endpar
dynamicAssert(delay.ready == False, "delay line still ready after value yield");
endseq;
endfunction
let delay0 <- mkDelayLine(0);
lib: add more documentation
2024-08-14 05:53:47 +02:00
let delay1 <- mkDelayLine(1);
let delay2 <- mkDelayLine(2);
let delay3 <- mkDelayLine(3);
let delay4 <- mkDelayLine(4);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
lib: add more documentation
2024-08-14 05:53:47 +02:00
let test0 = seq
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
dynamicAssert(delay0.ready == False, "delay line ready before put");
par
action
delay0 <= 42;
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
endaction
action
dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
lib/DelayLine: plumb verbose test flag into tests
2024-09-09 20:20:09 +02:00
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
endaction
dynamicAssert(delay0 == 42, "delay line has wrong value");
endpar
dynamicAssert(delay0.ready == False, "delay line ready without write");
endseq;
lib: add more documentation
2024-08-14 05:53:47 +02:00
runTest(100,
mkTest("DelayLine", seq
mkTest("DelayLine/0", test0);
mkTest("DelayLine/1", testDelayLine(delay1, 1));
mkTest("DelayLine/2", testDelayLine(delay2, 2));
mkTest("DelayLine/3", testDelayLine(delay3, 3));
mkTest("DelayLine/4", testDelayLine(delay4, 4));
endseq));
lib: add a DelayLine module A delay line takes a write and echoes it back N cycles later, with N fixed at compile time. It's a handy primitive to have when wrapping Verilog blackbox modules because the blackbox often specifies something like having 2 cycles of latency, and so you need to bubble the fact that a write occurred 2 cycles ago through to the output so that you can wire up the right implicit conditions.
2024-08-14 05:53:47 +02:00
endmodule
endpackage