gary/sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v

module tb_DP16KD_18b_sync_nowriteout_unregistered();
  reg CLKA=0, RSTA=0, CEA=0, OCEA=0, WEA=0;
  reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
  reg [2:0] CSA=0, CSB=0;
  reg [13:0] ADA, ADB;
  reg [17:0] DIA, DIB;
  wire [17:0] DOA, DOB;
  reg [239:0] TESTNAME;

  DP16KD ram(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
             .CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
             .ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]), .ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]), .ADA3(ADA[3]), .ADA2(ADA[2]), .ADA1(ADA[1]), .ADA0(ADA[0]),
             .DIA17(DIA[17]), .DIA16(DIA[16]), .DIA15(DIA[15]), .DIA14(DIA[14]), .DIA13(DIA[13]), .DIA12(DIA[12]), .DIA11(DIA[11]), .DIA10(DIA[10]), .DIA9(DIA[9]), .DIA8(DIA[8]), .DIA7(DIA[7]), .DIA6(DIA[6]), .DIA5(DIA[5]), .DIA4(DIA[4]), .DIA3(DIA[3]), .DIA2(DIA[2]), .DIA1(DIA[1]), .DIA0(DIA[0]),
             .DOA17(DOA[17]), .DOA16(DOA[16]), .DOA15(DOA[15]), .DOA14(DOA[14]), .DOA13(DOA[13]), .DOA12(DOA[12]), .DOA11(DOA[11]), .DOA10(DOA[10]), .DOA9(DOA[9]), .DOA8(DOA[8]), .DOA7(DOA[7]), .DOA6(DOA[6]), .DOA5(DOA[5]), .DOA4(DOA[4]), .DOA3(DOA[3]), .DOA2(DOA[2]), .DOA1(DOA[1]), .DOA0(DOA[0]),

             .CLKB(CLKB), .RSTB(RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
             .CSB2(CSB[2]), .CSB1(CSB[1]), .CSB0(CSB[0]),
             .ADB13(ADB[13]), .ADB12(ADB[12]), .ADB11(ADB[11]), .ADB10(ADB[10]), .ADB9(ADB[9]), .ADB8(ADB[8]), .ADB7(ADB[7]), .ADB6(ADB[6]), .ADB5(ADB[5]), .ADB4(ADB[4]), .ADB3(ADB[3]), .ADB2(ADB[2]), .ADB1(ADB[1]), .ADB0(ADB[0]),
             .DIB17(DIB[17]), .DIB16(DIB[16]), .DIB15(DIB[15]), .DIB14(DIB[14]), .DIB13(DIB[13]), .DIB12(DIB[12]), .DIB11(DIB[11]), .DIB10(DIB[10]), .DIB9(DIB[9]), .DIB8(DIB[8]), .DIB7(DIB[7]), .DIB6(DIB[6]), .DIB5(DIB[5]), .DIB4(DIB[4]), .DIB3(DIB[3]), .DIB2(DIB[2]), .DIB1(DIB[1]), .DIB0(DIB[0]),
             .DOB17(DOB[17]), .DOB16(DOB[16]), .DOB15(DOB[15]), .DOB14(DOB[14]), .DOB13(DOB[13]), .DOB12(DOB[12]), .DOB11(DOB[11]), .DOB10(DOB[10]), .DOB9(DOB[9]), .DOB8(DOB[8]), .DOB7(DOB[7]), .DOB6(DOB[6]), .DOB5(DOB[5]), .DOB4(DOB[4]), .DOB3(DOB[3]), .DOB2(DOB[2]), .DOB1(DOB[1]), .DOB0(DOB[0]));

  always begin
    #5
    CLKA <= !CLKA;
    CLKB <= !CLKB;
  end

  initial begin
    $dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered");
    $dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered);
    #10
    // Write to lowest and highest addrs, read back from the other port.
    TESTNAME="SIMPLE WRITE/READ 1";
    ADA=0; DIA=42; CEA=1; WEA=1; // Write min addr
    ADB=1023; DIB=18'h3FFFF; CEB=1; WEB=1; // write max addr
    #10
    ADA=1023; DIA=0; CEA=1; WEA=0; // Read max addr
    ADB=0;    DIB=0; CEB=1; WEB=0; // Read min addr
    #10
    // Swap values around, read back from other port.
    TESTNAME="SIMPLE WRITE/READ 2";
    ADA=1023; DIA=42;        CEA=1; WEA=1; // Write max addr
    ADB=0;    DIB=18'h3FFFF; CEB=1; WEB=1; // Write min addr
    #10
    ADA=0;    DIA=0; CEA=1; WEA=0; // Read min addr
    ADB=1023; DIB=0; CEB=1; WEB=0; // Read max addr
    #10
    // No change when reading and not enabled
    TESTNAME="NOT ENABLED";
    ADA=1023; DIA=0; CEA=0; WEA=0;
    ADB=0;    DIA=0; CEB=0; WEB=0;
    #10
    // Output changes again with chip enabled
    CEA=1;
    CEB=1;
    #10
    // Same if another chip is selected
    TESTNAME="NOT SELECTED";
    ADA=1023; DIA=0; WEA=0; CSA=3;
    ADB=0;    DIB=0; WEB=0; CSB=2;
    #10
    // Output changes again with chip enabled
    CSA=0;
    CSB=0;
    #10
    // Reset clears regs, overrules input, doesn't affect other port,
    // doesn't affect memory contents.
    TESTNAME="RESET A";
    ADA=0; RSTA=1;
    #10
    RSTA=0;
    #10
    TESTNAME="RESET B";
    ADB=1023; RSTB=1;
    #10
    RSTB=0;
    #10
    // Write-write conflict writes undef value
    TESTNAME="WRITE/WRITE CONFLICT";
    ADA=0; DIA=0;         WEA=1;
    ADB=0; DIB=18'h3FFFF; WEB=1;
    #10
    WEA=0;
    WEB=0;
    #10
    // Write-write conflict writes undef value
    TESTNAME="A READ/B WRITE CONFLICT";
    ADA=0; DIA=0;         WEA=0;
    ADB=0; DIB=18'h3FFFF; WEB=1;
    #10
    WEA=0;
    WEB=0;
    #10
    // Write-write conflict writes undef value
    TESTNAME="A WRITE/B READ CONFLICT";
    ADA=0; DIA=0;         WEA=1;
    ADB=0; DIB=18'h3FFFF; WEB=0;
    #10
    WEA=0;
    WEB=0;
    #10
    TESTNAME=240'bx;
    #10
    $finish;
  end
endmodule