gary/lib/DelayLine_Test.bsv

91 lines
2.9 KiB
Plaintext
Raw Permalink Normal View History

package DelayLine_Test;
import Assert::*;
import StmtFSM::*;
import Testing::*;
import Printf::*;
import List::*;
import DelayLine::*;
module mkTB();
let testflags <- mkTestFlags();
2024-08-14 05:53:47 +02:00
let cycles <- mkCycleCounter();
function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
seq
action
delay <= 42;
2024-08-14 05:53:47 +02:00
cycles.reset();
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
endaction
repeat (wantDelay-1)
action
if (delay.ready) begin
$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish;
end
endaction
// Check the value coming off the delay line and the timing
// separately, since the delay line read can be blocked by
// implicit conditions.
par
dynamicAssert(delay == 42, "delay output was wrong value");
action
dynamicAssert(delay.ready == True, "delay line not ready when expected");
2024-08-14 05:53:47 +02:00
if (cycles != wantDelay) begin
$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish;
end
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
endaction
endpar
dynamicAssert(delay.ready == False, "delay line still ready after value yield");
endseq;
endfunction
let delay0 <- mkDelayLine(0);
2024-08-14 05:53:47 +02:00
let delay1 <- mkDelayLine(1);
let delay2 <- mkDelayLine(2);
let delay3 <- mkDelayLine(3);
let delay4 <- mkDelayLine(4);
2024-08-14 05:53:47 +02:00
let test0 = seq
dynamicAssert(delay0.ready == False, "delay line ready before put");
par
action
delay0 <= 42;
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
endaction
action
dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
endaction
dynamicAssert(delay0 == 42, "delay line has wrong value");
endpar
dynamicAssert(delay0.ready == False, "delay line ready without write");
endseq;
2024-08-14 05:53:47 +02:00
runTest(100,
mkTest("DelayLine", seq
mkTest("DelayLine/0", test0);
mkTest("DelayLine/1", testDelayLine(delay1, 1));
mkTest("DelayLine/2", testDelayLine(delay2, 2));
mkTest("DelayLine/3", testDelayLine(delay3, 3));
mkTest("DelayLine/4", testDelayLine(delay4, 4));
endseq));
endmodule
endpackage