29 lines
1.0 KiB
Plaintext
29 lines
1.0 KiB
Plaintext
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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## LED indicators "blinkey" and "gpio" sheet
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LOCATE COMP "paint" SITE "H3";
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LOCATE COMP "hsync" SITE "E1";
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LOCATE COMP "vsync" SITE "E2";
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IOBUF PORT "paint" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "hsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "vsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "uart_rx_v" SITE "M1"; # FIRE1
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IOBUF PORT "uart_rx_v" PULLMODE=UP IO_TYPE=LVCMOS33;
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LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
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IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "wifi_gpio0" SITE "L2";
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IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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