From 9e6c1915ee50a90b2f5e9d77e23d3dc7b1eac9bd Mon Sep 17 00:00:00 2001
From: Kyle J Cardoza <Kyle.Cardoza@icloud.com>
Date: Sun, 14 Jul 2024 18:44:45 -0400
Subject: [PATCH] Fixed SRAM select logic and /RD timing bug in PLD

---
 PLD/Prototype 4/Sentinel 65X Prototype 4.chp | 0
 PLD/Prototype 4/Sentinel 65X Prototype 4.fus | 4 ++--
 PLD/Prototype 4/Sentinel 65X Prototype 4.jed | 7 ++++---
 PLD/Prototype 4/Sentinel 65X Prototype 4.pin | 0
 PLD/Prototype 4/Sentinel 65X Prototype 4.pld | 4 ++--
 5 files changed, 8 insertions(+), 7 deletions(-)
 mode change 100644 => 100755 PLD/Prototype 4/Sentinel 65X Prototype 4.chp
 mode change 100644 => 100755 PLD/Prototype 4/Sentinel 65X Prototype 4.fus
 mode change 100644 => 100755 PLD/Prototype 4/Sentinel 65X Prototype 4.jed
 mode change 100644 => 100755 PLD/Prototype 4/Sentinel 65X Prototype 4.pin
 mode change 100644 => 100755 PLD/Prototype 4/Sentinel 65X Prototype 4.pld

diff --git a/PLD/Prototype 4/Sentinel 65X Prototype 4.chp b/PLD/Prototype 4/Sentinel 65X Prototype 4.chp
old mode 100644
new mode 100755
diff --git a/PLD/Prototype 4/Sentinel 65X Prototype 4.fus b/PLD/Prototype 4/Sentinel 65X Prototype 4.fus
old mode 100644
new mode 100755
index 73dcdf9..aae0f62
--- a/PLD/Prototype 4/Sentinel 65X Prototype 4.fus	
+++ b/PLD/Prototype 4/Sentinel 65X Prototype 4.fus	
@@ -16,8 +16,8 @@ Pin 23 = /WR          S0 = 0   S1 = 1
 
 Pin 22 = /RD          S0 = 0   S1 = 1
  10  ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
- 11  x--- x--- ---- ---- ---- ---- ---- ---- ---- ---- ----
- 12  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+ 11  ---- x--- ---- ---- ---- ---- ---- ---- ---- ---- ----
+ 12  ---- -x-- ---- ---- ---- ---- ---- ---- ---- ---- ----
  13  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  14  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
  15  xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
diff --git a/PLD/Prototype 4/Sentinel 65X Prototype 4.jed b/PLD/Prototype 4/Sentinel 65X Prototype 4.jed
old mode 100644
new mode 100755
index 7698a9a..2419285
--- a/PLD/Prototype 4/Sentinel 65X Prototype 4.jed	
+++ b/PLD/Prototype 4/Sentinel 65X Prototype 4.jed	
@@ -8,7 +8,8 @@ Device:         GAL22V10
 *L0044 11111111111111111111111111111111111111111111
 *L0088 01111011111111111111111111111111111111111111
 *L0440 11111111111111111111111111111111111111111111
-*L0484 01110111111111111111111111111111111111111111
+*L0484 11110111111111111111111111111111111111111111
+*L0528 11111011111111111111111111111111111111111111
 *L0924 11111111111111111111111111111111111111111111
 *L0968 11111111101111111111111111111111111111111111
 *L1012 11111111111111111111101110111011011101111111
@@ -22,6 +23,6 @@ Device:         GAL22V10
 *L3124 11111111111110111111111111111111111101111111
 *L5808 01010100010100000000
 *L5828 0101001101000101010011100101010001001001010011100100010101001100
-*C53d6
+*C58d0
 *
-b9c8
+c3a2
diff --git a/PLD/Prototype 4/Sentinel 65X Prototype 4.pin b/PLD/Prototype 4/Sentinel 65X Prototype 4.pin
old mode 100644
new mode 100755
diff --git a/PLD/Prototype 4/Sentinel 65X Prototype 4.pld b/PLD/Prototype 4/Sentinel 65X Prototype 4.pld
old mode 100644
new mode 100755
index 7ef982d..ac1c0b5
--- a/PLD/Prototype 4/Sentinel 65X Prototype 4.pld	
+++ b/PLD/Prototype 4/Sentinel 65X Prototype 4.pld	
@@ -6,7 +6,7 @@ NC    NC   NC   NC   NC   /RAM1 /RAM0 /ROM1 /ROM0 /RD   /WR   VCC
 
 WR = PHI2 * /RW
 
-RD = PHI2 * RW
+RD = RW + /RW
 
 RAM0 = CS5 * /A19 * /A20 * /A21 * /A22 * /A23
 
@@ -22,4 +22,4 @@ ROM0 = CS4 +
 
 DESCRIPTION
 
-PLD Logic for the Sentinel 65X PLD
\ No newline at end of file
+PLD Logic for the Sentinel 65X PLD