249 lines
5.5 KiB
OpenEdge ABL
249 lines
5.5 KiB
OpenEdge ABL
|
||
AUTO_INC_NONE = $00
|
||
AUTO_INC_1 = $01
|
||
AUTO_INC_2 = $02
|
||
AUTO_INC_4 = $03
|
||
AUTO_INC_8 = $04
|
||
AUTO_INC_16 = $05
|
||
AUTO_INC_32 = $06
|
||
AUTO_INC_64 = $07
|
||
AUTO_INC_128 = $08
|
||
AUTO_INC_256 = $09
|
||
AUTO_INC_512 = $0A
|
||
AUTO_INC_40 = $0B
|
||
AUTO_INC_80 = $0C
|
||
AUTO_INC_160 = $0D
|
||
AUTO_INC_320 = $0E
|
||
AUTO_INC_640 = $0F
|
||
|
||
DISABLED = 0
|
||
ENABLED = 1
|
||
|
||
VERA_L_BPP1 = %00000000
|
||
VERA_L_BPP2 = %00000001
|
||
VERA_L_BPP4 = %00000010
|
||
VERA_L_BPP8 = %00000011
|
||
|
||
VERA_L_BITMAP = %00000100
|
||
VERA_L_T256C = %00001000
|
||
|
||
VERA_L_32W = %00000000
|
||
VERA_L_64W = %00010000
|
||
VERA_L_128W = %00100000
|
||
VERA_L_256W = %00110000
|
||
|
||
VERA_L_32H = %00000000
|
||
VERA_L_64H = %01000000
|
||
VERA_L_128H = %10000000
|
||
VERA_L_256H = %11000000
|
||
|
||
VERA_TILESIZE8x8 = %00000000
|
||
VERA_TILESIZE16x8 = %00000001
|
||
VERA_TILESIZE8x16 = %00000010
|
||
VERA_TILESIZE16x16 = %00000011
|
||
|
||
; The base address of the VERA chip
|
||
VERA_BASE = $00DF00
|
||
|
||
; Offsets (relative to VERA_BASE) for each VERA register
|
||
|
||
VERA_ADDRx_L = VERA_BASE + 00
|
||
VERA_ADDRx_M = VERA_BASE + 01
|
||
VERA_ADDRx_H = VERA_BASE + 02
|
||
|
||
; Accssible with ADDRSEL == 0
|
||
VERA_ADDR0_L = VERA_BASE + 00
|
||
VERA_ADDR0_M = VERA_BASE + 01
|
||
VERA_ADDR0_H = VERA_BASE + 02
|
||
|
||
; Accssible with ADDRSEL == 1
|
||
VERA_ADDR1_L = VERA_BASE + 00
|
||
VERA_ADDR1_M = VERA_BASE + 01
|
||
VERA_ADDR1_H = VERA_BASE + 02
|
||
|
||
VERA_DATA0 = VERA_BASE + $03
|
||
VERA_DATA1 = VERA_BASE + $04
|
||
|
||
VERA_CTRL = VERA_BASE + $05
|
||
VERA_IEN = VERA_BASE + $06
|
||
VERA_ISR = VERA_BASE + $06
|
||
VERA_IRQLINE_L = VERA_BASE + $07
|
||
VERA_SCANLINE_L = VERA_BASE + $08
|
||
|
||
; Accssible with DCSEL == 0
|
||
VERA_DC_VIDEO = VERA_BASE + $09
|
||
VERA_DC_HSCALE = VERA_BASE + $0A
|
||
VERA_DC_VSCALE = VERA_BASE + $0B
|
||
VERA_DC_BORDER = VERA_BASE + $0C
|
||
|
||
; Accssible with DCSEL == 1
|
||
VERA_DC_HSTART = VERA_BASE + $09
|
||
VERA_DC_HSTOP = VERA_BASE + $0A
|
||
VERA_DC_VSTART = VERA_BASE + $0B
|
||
VERA_DC_VSTOP = VERA_BASE + $0C
|
||
|
||
; Layer 0
|
||
VERA_L0_CONFIG = VERA_BASE + $0D
|
||
VERA_L0_MAPBASE = VERA_BASE + $0E
|
||
VERA_L0_TILEBASE = VERA_BASE + $0F
|
||
VERA_L0_HSCROLL_L = VERA_BASE + $10
|
||
VERA_L0_HSCROLL_H = VERA_BASE + $11
|
||
VERA_L0_VSCROLL_L = VERA_BASE + $12
|
||
VERA_L0_VSCROLL_H = VERA_BASE + $13
|
||
|
||
; Layer 1
|
||
VERA_L1_CONFIG = VERA_BASE + $14
|
||
VERA_L1_MAPBASE = VERA_BASE + $15
|
||
VERA_L1_TILEBASE = VERA_BASE + $16
|
||
VERA_L1_HSCROLL_L = VERA_BASE + $17
|
||
VERA_L1_HSCROLL_H = VERA_BASE + $18
|
||
VERA_L1_VSCROLL_L = VERA_BASE + $19
|
||
VERA_L1_VSCROLL_H = VERA_BASE + $1A
|
||
|
||
; Audio
|
||
VERA_AUDIO_CTRL = VERA_BASE + $1B
|
||
VERA_AUDIO_RATE = VERA_BASE + $1C
|
||
VERA_AUDIO_DATA = VERA_BASE + $1D
|
||
|
||
; SPI (Unused in prototype four!)
|
||
VERA_SPI_DATA = VERA_BASE + $1E
|
||
VERA_SPI_CTRL = VERA_BASE + $1F
|
||
|
||
; VRAM layout
|
||
TEXT_CONSOLE_TILES = $0800
|
||
TEXT_CONSOLE0_VRAM = $1800
|
||
VERA_PSG_BASE = $1F9C0
|
||
VERA_PALETTE_BASE = $1FA00
|
||
VERA_SPRITE_ATTR_BASE = $1FC00
|
||
|
||
; vera_address_select - selects the active VERA address register
|
||
; Selecting 0 means that the address registers control the address
|
||
; accessed by VERA_DATA0, while selecting 1 means controlling the
|
||
; address for VERA_DATA1.
|
||
vera_address_select .macro value
|
||
pha
|
||
|
||
lda #(\value & %00000001)
|
||
tsb VERA_CTRL
|
||
|
||
pla
|
||
.endmacro
|
||
|
||
; vera_address_set - sets the address registers to the passed in value
|
||
vera_address_set .macro addr
|
||
pha
|
||
|
||
lda #>\addr
|
||
sta VERA_ADDRx_L
|
||
|
||
lda #<\addr
|
||
sta VERA_ADDRx_M
|
||
|
||
lda #`\addr
|
||
sta VERA_ADDRx_H
|
||
|
||
pla
|
||
.endmacro
|
||
|
||
; vera_address_incr - set the VERA address auto-increment.
|
||
vera_address_incr .macro increment
|
||
pha
|
||
|
||
; Clear the top four bits of ADDRx_H (increment value and decrement bit)
|
||
lda #%11111000
|
||
trb VERA_ADDRx_H
|
||
|
||
; Set the new value
|
||
lda #\increment << 4
|
||
tsb VERA_ADDRx_H
|
||
|
||
pla
|
||
.endmacro
|
||
|
||
; vera_address_decr - set the VERA address auto-decrement.
|
||
vera_address_decr .macro decrement
|
||
pha
|
||
|
||
; Clear the top five bits of ADDRx_H
|
||
lda #%11110000
|
||
trb VERA_ADDRx_H
|
||
|
||
; Set the new value (and the decrement bit)
|
||
lda #(\increment << 4) | %00001000
|
||
tsb VERA_ADDRx_H
|
||
|
||
pla
|
||
.endmacro
|
||
|
||
; Copies up to 64KB of two-byte data to VERA memory, beginning at
|
||
; the provided address in VERA's address space.
|
||
;
|
||
; Arguments:
|
||
; target: The address in VERA memory at which the
|
||
; copied data will begin
|
||
; source: The address in CPU memory at which the data
|
||
; to be copied begins
|
||
; length: The number of bytes to copy to VERA memory. Must
|
||
; be a multiple of 2.
|
||
vera_write .macro target, source, length
|
||
.save_registers
|
||
|
||
; Set up the address/data VERA registers for 16-bit copying.
|
||
|
||
.vera_address_select 0
|
||
.vera_address_set \{target}
|
||
.vera_address_incr AUTO_INC_2
|
||
.vera_address_select 1
|
||
.vera_address_set \{target} + 1
|
||
.vera_address_incr AUTO_INC_2
|
||
|
||
.long_a
|
||
|
||
ldx #0
|
||
copy_loop:
|
||
lda \{source},X
|
||
sta VERA_DATA0
|
||
inx
|
||
inx
|
||
cpx #\{length}
|
||
beq copy_loop
|
||
|
||
.restore_registers
|
||
.endmacro
|
||
|
||
; Copies up to 64KB of two-byte data to CPU memory from VERA
|
||
; memory.
|
||
;
|
||
; Arguments:
|
||
; target: The address in CPU memory at which the
|
||
; copied data will begin
|
||
; source: The address in VERA memory at which the data
|
||
; to be copied begins
|
||
; length: The number of bytes to copy from VERA memory. Must
|
||
; be a multiple of 2.
|
||
vera_read .macro target, source, length
|
||
.save_registers
|
||
|
||
; Set up the address/data VERA registers for 16-bit copying.
|
||
|
||
.vera_address_select 0
|
||
.vera_address_set \{source}
|
||
.vera_address_incr AUTO_INC_2
|
||
.vera_address_select 1
|
||
.vera_address_set \{source} + 1
|
||
.vera_address_incr AUTO_INC_2
|
||
|
||
.long_a
|
||
|
||
ldx #0
|
||
copy_loop:
|
||
lda VERA_DATA0
|
||
sta \{target},X
|
||
inx
|
||
inx
|
||
cpx #\{length}
|
||
beq copy_loop
|
||
|
||
.restore_registers
|
||
.endmacro
|