AUTO_NONE = $000000 AUTO_INC_1 = $100000 AUTO_INC_2 = $200000 AUTO_INC_4 = $300000 AUTO_INC_8 = $400000 AUTO_INC_16 = $500000 AUTO_INC_32 = $600000 AUTO_INC_64 = $700000 AUTO_INC_128 = $800000 AUTO_INC_256 = $900000 AUTO_INC_512 = $A00000 AUTO_INC_40 = $B00000 AUTO_INC_80 = $C00000 AUTO_INC_160 = $D00000 AUTO_INC_320 = $E00000 AUTO_INC_640 = $F00000 DISABLED = 0 ENABLED = 1 VERA_L_BPP1 = %00000000 VERA_L_BPP2 = %00000001 VERA_L_BPP4 = %00000010 VERA_L_BPP8 = %00000011 VERA_L_BITMAP = %00000100 VERA_L_T256C = %00001000 VERA_L_32W = %00000000 VERA_L_64W = %00010000 VERA_L_128W = %00100000 VERA_L_256W = %00110000 VERA_L_32H = %00000000 VERA_L_64H = %01000000 VERA_L_128H = %10000000 VERA_L_256H = %11000000 VERA_TILESIZE8x8 = %00000000 VERA_TILESIZE16x8 = %00000001 VERA_TILESIZE8x16 = %00000010 VERA_TILESIZE16x16 = %00000011 ; The base address of the VERA chip VERA_BASE = $00DF00 ; Offsets (relative to VERA_BASE) for each VERA register VERA_ADDRx_L = VERA_BASE + 00 VERA_ADDRx_M = VERA_BASE + 01 VERA_ADDRx_H = VERA_BASE + 02 ; Accssible with ADDRSEL == 0 VERA_ADDR0_L = VERA_BASE + 00 VERA_ADDR0_M = VERA_BASE + 01 VERA_ADDR0_H = VERA_BASE + 02 ; Accssible with ADDRSEL == 1 VERA_ADDR1_L = VERA_BASE + 00 VERA_ADDR1_M = VERA_BASE + 01 VERA_ADDR1_H = VERA_BASE + 02 VERA_DATA_0 = VERA_BASE + $03 VERA_DATA_1 = VERA_BASE + $04 VERA_CTRL = VERA_BASE + $05 VERA_IEN = VERA_BASE + $06 VERA_ISR = VERA_BASE + $07 VERA_IRQLINE_L = VERA_BASE + $08 VERA_SCANLINE_L = VERA_BASE + $08 ; Accssible with DCSEL == 0 VERA_DC_VIDEO = VERA_BASE + $09 VERA_DC_HSCALE = VERA_BASE + $0A VERA_DC_VSCALE = VERA_BASE + $0B VERA_DC_BORDER = VERA_BASE + $0C ; Accssible with DCSEL == 1 VERA_DC_HSTART = VERA_BASE + $09 VERA_DC_HSTOP = VERA_BASE + $0A VERA_DC_VSTART = VERA_BASE + $0B VERA_DC_VSTOP = VERA_BASE + $0C ; Layer 0 VERA_L0_CONFIG = VERA_BASE + $0D VERA_L0_MAPBASE = VERA_BASE + $0E VERA_L0_TILEBASE = VERA_BASE + $0F VERA_L0_HSCROLL_L = VERA_BASE + $10 VERA_L0_HSCROLL_H = VERA_BASE + $11 VERA_L0_VSCROLL_L = VERA_BASE + $12 VERA_L0_VSCROLL_H = VERA_BASE + $13 ; Layer 1 VERA_L1_CONFIG = VERA_BASE + $14 VERA_L1_MAPBASE = VERA_BASE + $15 VERA_L1_TILEBASE = VERA_BASE + $16 VERA_L1_HSCROLL_L = VERA_BASE + $17 VERA_L1_HSCROLL_H = VERA_BASE + $18 VERA_L1_VSCROLL_L = VERA_BASE + $19 VERA_L1_VSCROLL_H = VERA_BASE + $1A ; Audio VERA_AUDIO_CTRL = VERA_BASE + $1B VERA_AUDIO_RATE = VERA_BASE + $1C VERA_AUDIO_DATA = VERA_BASE + $1D ; SPI (Unused in prototype four!) VERA_SPI_DATA = VERA_BASE + $1E VERA_SPI_CTRL = VERA_BASE + $1F ; VRAM layout TEXT_CONSOLE_TILES = $000800 TEXT_CONSOLE0_VRAM = $001800 ; Runs up to $5800 TEXT_CONSOLE_SPRITE_BITMAPS = $005800 VERA_PSG_BASE = $01F9C0 VERA_PALETTE_BASE = $01FA00 VERA_SPRITE_ATTR_BASE = $01FC00 vera_address_select .macro value .save_registers lda VERA_CTRL .if \{value} > 0 ora #%00000001 .else and #%11111110 .endif sta VERA_CTRL .restore_registers .endmacro ; vset - sets the address registers to the passed in value vera_address_set .macro addr php sep #$20 .as lda #<\{addr} sta VERA_ADDRx_L lda #>\{addr} sta VERA_ADDRx_M lda #`\{addr} sta VERA_ADDRx_H plp .endmacro vera_reg_write .macro reg, value .save_registers lda #\{value} sta \{reg} .restore_registers .endmacro vera_mem_write .macro dest, src, length .save_registers .vera_address_select 0 .vera_address_set \{dest} | AUTO_INC_1 ldx #0 copy_loop: lda \{src}, X sta VERA_DATA_0 inx cpx #\{length} bne copy_loop .restore_registers .endmacro vera_mem_set .macro dest, value, length .save_registers .vera_address_select 0 .vera_address_set \{dest} | AUTO_INC_1 lda #\{value} ldx #0 copy_loop: sta VERA_DATA_0 inx cpx #\{length} bne copy_loop .restore_registers .endmacro vera_mem_read .macro dest, src, length .save_registers .vera_address_select 0 .vera_address_set \{src} | AUTO_INC_1 ldx #0 copy_loop: lda \{VERA_DATA_0} sta \{dest}, X inx cpx #\{length} bne copy_loop .restore_registers .endmacro