diff --git a/Makefile b/Makefile index cead62d..c33616a 100644 --- a/Makefile +++ b/Makefile @@ -16,6 +16,7 @@ SOURCES := src/memory.s \ src/main.s \ src/boot.s \ src/irq.s \ + src/led.s \ src/vera.s INCLUDES := $(wildcard include/*.i) diff --git a/include/w65c265s.i b/include/w65c265s.i index 8f3945c..3611ecd 100644 --- a/include/w65c265s.i +++ b/include/w65c265s.i @@ -2,6 +2,7 @@ PD0 = $00DF00 PD1 = $00DF01 PD2 = $00DF02 PD3 = $00DF03 + PDD0 = $00DF04 PDD1 = $00DF05 PDD2 = $00DF06 @@ -14,10 +15,11 @@ PD7 = $00DF23 PDD4 = $00DF24 PDD5 = $00DF25 PDD6 = $00DF26 -PCS7 = $00DF27 +PCS7 = $00DF27 BCR = $00DF40 SSCR = $00DF41 + TCR = $00DF42 TER = $00DF43 TIFR = $00DF44 @@ -68,6 +70,7 @@ ACSR2 = $00DF74 ARTD2 = $00DF75 ACSR3 = $00DF76 ARTD3 = $00DF77 + PIBFR = $00DF78 PIBER = $00DF79 PIR2 = $00DF7A @@ -75,4 +78,45 @@ PIR3 = $00DF7B PIR4 = $00DF7C PIR5 = $00DF7D PIR6 = $00DF7E -PIR7 = $00DF7F \ No newline at end of file +PIR7 = $00DF7F + +; Enable the 512 bytes of on-CPU SRAM from $000000-0001FF +w65c265s_sram_on .macro + lda #%00000100 + trb SSCR +.endmacro + +w65c265s_sram_off .macro + lda #%00000100 + tsb SSCR +.endmacro + +; Disable the on-CPU ROM +w65c265s_rom_off .macro + lda #%10000000 + tsb BCR +.endmacro + +; Enable the on-CPU ROM +w65c265s_rom_on .macro + lda #%10000000 + trb BCR +.endmacro + +; Start FCLK +fclk_start .macro + lda #%00000001 + tsb SSCR +.endmacro + +; Stop FCLK +fclk_stop .macro + lda #%00000001 + trb SSCR +.endmacro + +; Select FCLK as the clock source +fclk_select .macro + lda #%11111010 + tsb SSCR +.endmacro \ No newline at end of file diff --git a/include/w65c816.i b/include/w65c816.i index 78e4550..afbb9ca 100644 --- a/include/w65c816.i +++ b/include/w65c816.i @@ -22,3 +22,22 @@ short_i .macro sep #$10 .xs .endmacro + +save_registers .macro + php + .long_a + .long_i + pha + phx + phy +.endmacro + +restore_registers .macro + .long_a + .long_i + ply + plx + pla + plp +.endmacro + \ No newline at end of file diff --git a/kernel.list b/kernel.list index 25f8230..23eea02 100644 --- a/kernel.list +++ b/kernel.list @@ -12,6 +12,7 @@ SSCR = $00df41 UIER = $00df49 AUTO_INC_256 = $900000 AUTO_INC_128 = $800000 +led_blink_red = $c1004d VERA_DC_VIDEO = 57097 VERA_DC_HSCALE = 57098 AUTO_INC_NONE = $000000 @@ -19,26 +20,27 @@ main = $c0ffc0 AUTO_INC_40 = $b00000 VERA_DC_VSCALE = 57099 VERA_CTRL = 57093 +VERA_L_128H = $80 EIER = $00df47 T2CH = $00df65 T0CH = $00df61 +VERA_PSG_BASE = $1f9c0 T0CL = $00df60 VERA_L0_MAPBASE = 57102 -AUTO_INC_2 = $200000 -AUTO_INC_1 = $100000 +VERA_PALETTE_BASE= $1fa00 +led_red_on = $c10019 VERA_AUDIO_DATA = 57117 VERA_TILESIZE8x8= $00 -AUTO_INC_16 = $500000 VERA_SCANLINE_L = 57096 T4LH = $00df59 T4LL = $00df58 TER = $00df43 UIFR = $00df48 -VERA_PSG_BASE = $1f9c0 +VERA_DC_HSTOP = 57098 VERA_ADDR1_L = 57088 PD7 = $00df23 PD6 = $00df22 -VERA_DC_HSTOP = 57098 +PD5 = $00df21 PD4 = $00df20 PD3 = $00df03 PD2 = $00df02 @@ -49,7 +51,6 @@ AUTO_INC_64 = $700000 VERA_AUDIO_RATE = 57116 ACSR0 = $00df70 VERA_BASE = $00df00 -ACSR2 = $00df74 ACSR3 = $00df76 T4CL = $00df68 T6CH = $00df6d @@ -71,23 +72,25 @@ PDD0 = $00df04 PDD1 = $00df05 PDD2 = $00df06 PDD3 = $00df07 -w65c265s_init = $008008 -VERA_L_128H = $80 +AUTO_INC_2 = $200000 +AUTO_INC_1 = $100000 VERA_DC_VSTART = 57099 -VERA_L_BPP8 = $03 +led_init = $c0fffa VERA_DATA0 = 57091 AUTO_INC_4 = $300000 AUTO_INC_8 = $400000 T7LL = $00df5e +led_red_off = $c10033 VERA_L_32W = $00 VERA_L_128W = $20 +AUTO_INC_16 = $500000 PIBFR = $00df78 AUTO_INC_32 = $600000 VERA_L0_CONFIG = 57101 VERA_DC_BORDER = 57100 T7CH = $00df6f AUTO_INC_160 = $d00000 -vera_init = $c0ffee +vera_init = $c10071 T2LL = $00df54 TIFR = $00df44 T2LH = $00df55 @@ -109,7 +112,7 @@ VERA_SPI_DATA = 57118 T2CL = $00df64 VERA_ADDR0_H = 57090 VERA_SPI_CTRL = 57119 -VERA_PALETTE_BASE= $1fa00 +VERA_L_BPP8 = $03 VERA_ADDR0_M = 57089 VERA_ADDR0_L = 57088 VERA_L_BPP4 = $02 @@ -123,18 +126,20 @@ T5LL = $00df5a VERA_TILESIZE8x16= $02 VERA_ISR = 57094 irq_exit = $00810d +w65c265s_init = $008008 VERA_ADDR1_M = 57089 UART3_BAUD_RATE = 9600 ACSR1 = $00df72 VERA_DC_VSTOP = 57100 VERA_L_32H = $00 -VERA_L_BITMAP = $04 +ACSR2 = $00df74 VERA_IRQLINE_L = 57095 T6LL = $00df5c PDD4 = $00df24 T3CL = $00df66 T3CH = $00df67 VERA_L1_MAPBASE = 57109 +delay = $c0ffee VERA_L0_HSCROLL_L= 57104 VERA_L0_HSCROLL_H= 57105 T6LH = $00df5d @@ -153,6 +158,7 @@ empty_irq_handler= $008100 VERA_TILESIZE16x8= $01 VERA_AUDIO_CTRL = 57115 VERA_DC_HSTART = 57097 +VERA_L_BITMAP = $04 DISABLED = 0 ARTD2 = $00df75 ARTD3 = $00df77 @@ -161,6 +167,5 @@ ARTD1 = $00df73 T1LH = $00df53 VERA_SPRITE_ATTR_BASE= $1fc00 BCR = $00df40 -PD5 = $00df21 VERA_L1_VSCROLL_L= 57113 VERA_L1_VSCROLL_H= 57114 diff --git a/src/led.s b/src/led.s new file mode 100644 index 0000000..4c929b1 --- /dev/null +++ b/src/led.s @@ -0,0 +1,140 @@ +.section code + +led_init .proc + .save_registers + .short_a + .long_i + + ; Set P5.4 and P5.5 as output + lda #%00110000 + tsb PDD5 + + ; Set P6.1 as output + lda #%00000010 + tsb PDD6 + + .restore_registers + rtl +.endproc + +led_red_on .proc + .save_registers + .short_a + .long_i + + lda #%00010000 + tsb PD5 + + .restore_registers + rtl +.endproc + +led_red_off .proc + .save_registers + .short_a + .long_i + + lda #%00010000 + trb PD5 + + .restore_registers + rtl +.endproc + +led_green_on .proc + .save_registers + .short_a + .long_i + + lda #%00100000 + tsb PD5 + + .restore_registers + rtl +.endproc + +led_green_off .proc + .save_registers + .short_a + .long_i + + lda #%00100000 + trb PD5 + + .restore_registers + rtl +.endproc + +led_blue_on .proc + .save_registers + .short_a + .long_i + + lda #%00000010 + tsb PD6 + + .restore_registers + rtl +.endproc + +led_blue_off .proc + .save_registers + .short_a + .long_i + + lda #%00000010 + trb PD6 + + .restore_registers + rtl +.endproc + +led_blink_red .proc + .save_registers + .short_a + .long_i + + jsl led_red_on + + ldx #02 + jsl delay + + jsl led_red_off + + .restore_registers + rtl +.endproc + +led_blink_green .proc + .save_registers + .short_a + .long_i + + jsl led_green_on + + ldx #02 + jsl delay + + jsl led_green_off + + .restore_registers + rtl +.endproc + +led_blink_blue .proc + .save_registers + .short_a + .long_i + + jsl led_blue_on + + ldx #02 + jsl delay + + jsl led_blue_off + + .restore_registers + rtl +.endproc + +.endsection code \ No newline at end of file diff --git a/src/main.s b/src/main.s index 19fe620..cd85731 100644 --- a/src/main.s +++ b/src/main.s @@ -1,13 +1,12 @@ .section code main .proc - ; Start FCLK - lda #%00000001 - tsb SSCR + .short_a + .long_i - ; Disable the on-CPU ROM - lda #%10001001 - tsb BCR + .fclk_start + + .w65c265s_rom_off ; Disable secondary interrupt sources stz UIER @@ -17,23 +16,36 @@ main .proc ; Disable all timers stz TER - ; Set P5.4 and P5.5 as output - lda #%00110000 - tsb PDD5 + .fclk_select - ; Set P6.1 as output - lda #%00000010 - tsb PDD6 + jsl led_blink_red - ; Disable on-chip SRAM - lda #%00000100 - tsb SSCR - - ; Select FCLK as the clock source - lda #%11111010 - tsb SSCR + jsl led_init ; Initialize the VERA jsl vera_init + +idle: + wai + bra idle .endproc + +; Delay X times. +delay .proc + phy + +loop_x + ldy #$FFFF + +loop_y + dey + bne loop_y + + dex + bne loop_x + + ply + rtl +.endproc + .endsection diff --git a/src/memory.s b/src/memory.s index ccd815c..669dbb7 100644 --- a/src/memory.s +++ b/src/memory.s @@ -15,6 +15,9 @@ .include "sentinel65x.i" +; The kernel uses its own direct page and stack, located in the on-CPU +; SRAM; this RAM is only visible during a kernel call, usually an interrupt +; handler, such as a timer or COP. * = 000000 .dsection zp diff --git a/stuff.s b/stuff.s deleted file mode 100644 index 8c3c0f6..0000000 --- a/stuff.s +++ /dev/null @@ -1,209 +0,0 @@ -.include "sentinel65x.i" - -* = $C8000 - -.null "WDC" - jml w65c265s_init - -w65c265s_init .proc - ; Disable standard interrupts - sei - - .short_a - .long_i - - ; Set data bank to 0 - lda #0 - pha - plb - .databank 0 - - ; Set direct page to $0000 - pea $0000 - pld - .dpage $0000 - - ; Set stack to $001FF - ldx #$01FF - txs - - ; Start FCLK - lda #%00000001 - tsb SSCR - - ; Disable the on-CPU ROM - lda #%10001001 - tsb BCR - - ; Disable secondary interrupt sources - stz UIER - stz TIER - stz EIER - - ; Enable all used chip select lines. - lda #%11110011 - sta PCS7 - - ; Disable all timers - stz TER - - ; Set P5.4 and P5.5 as output - lda #%00110000 - tsb PDD5 - - ; Set P6.1 as output - lda #%00000010 - tsb PDD6 - - ; Disable on-chip SRAM - lda #%00000100 - tsb SSCR - - ; Select FCLK as the clock source - lda #%11111010 - tsb SSCR - - ; Initialize the VERA - jsl vera_init - - ; Jump to entry point. - jml start -.endproc - -blink_red .proc - pha - phx - - ; Turn on the red LED - lda #%00010000 - tsb PD5 - - ldx #02 - jsl delay - - ; Turn off the red LED - lda #%00010000 - trb PD5 - - plx - pla - rtl -.endproc - -blink_green .proc - pha - phx - - ; Turn on the green LED - lda #%00100000 - tsb PD5 - - ldx #02 - jsl delay - - ; Turn off the green LED - lda #%00100000 - trb PD5 - - plx - pla - rtl -.endproc - -blink_blue .proc - pha - phx - - ; Turn on the blue LED - lda #%00000010 - tsb PD6 - - ldx #02 - jsl delay - - ; Turn off the blue LED - lda #%00000010 - trb PD6 - - plx - pla - rtl -.endproc - -; Delay X times. -delay .proc - phy - -loop_x - ldy #$FFFF - -loop_y - dey - bne loop_y - - dex - bne loop_x - - ply - rtl -.endproc - -start .proc - jsl blink_blue -main_loop - nop - bra main_loop -.endproc - -empty_irq_handler .proc - phb - phd - .long_a - .long_i - pha - phx - phy - - jmp irq_exit -.endproc - -nmi_handler .proc - - jsl blink_red - jsl blink_green - jsl blink_blue - - rti -.endproc - -irq_exit .proc - .long_a - .long_i - ply - plx - pla - pld - plb - rti -.endproc - -vera_init .proc - pha - - jsl blink_red - - - - jsl blink_green - - pla - rtl -.endproc - -.fill $FF80 - *, 0 -* = $FF80 -.fill $FFBA - *, empty_irq_handler -* = $FFBA -.word nmi_handler -.fill $FFFF - *, empty_irq_handler -.fill 524288 - *, 0