diff --git a/include/vera.i b/include/vera.i
index 712db2c..a095cd0 100644
--- a/include/vera.i
+++ b/include/vera.i
@@ -110,6 +110,8 @@ VERA_SPI_DATA = VERA_BASE + $1E
 VERA_SPI_CTRL = VERA_BASE + $1F
 
 ; VRAM layout
+TEXT_CONSOLE_TILES = $0800
+TEXT_CONSOLE0_VRAM = $1800
 VERA_PSG_BASE = $1F9C0
 VERA_PALETTE_BASE = $1FA00
 VERA_SPRITE_ATTR_BASE = $1FC00
diff --git a/src/vera.s b/src/vera.s
index 784842b..d048090 100644
--- a/src/vera.s
+++ b/src/vera.s
@@ -5,8 +5,117 @@ vera_init .proc
 
     jsl vera_reset
 
-    ; Load the VERA font. FIXME: target address is what?
-    ;.vera_memcpy $000000, vera_font_0, size(data.font_0)
+    stz $00DF05
+    lda #$11
+    sta $00DF09
+    stz $00DF0C
+    lda #$40
+    sta $00DF0A
+    sta $00DF0B
+
+    lda #02
+    sta $00DF05
+    stz $00DF09
+    lda #$A0
+    sta $00DF0A
+    stz $00DF0B
+    lda #$F0
+    sta $00DF0C
+
+    lda #$04
+    sta $00DF0D
+
+    lda #$11
+    sta $00DF02
+    lda #$FA
+    sta $00DF01
+    stz $00DF00
+    
+    lda #%11110000
+    sta $00DF03
+    lda #%00000000
+    sta $00DF03
+
+    lda #%00000000
+    sta $00DF03
+    lda #%00001111
+    sta $00DF03
+
+    lda #$10
+    sta $00DF02
+    stz $00DF01
+    stz $00DF00
+
+    .rept 40
+    lda #$80
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$80
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    stz $00DF03
+    .endrept
+
+    .rept 40
+    lda #$AA
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$55
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$AA
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$55
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$AA
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    lda #$55
+    sta $00DF03
+    .endrept
+
+    .rept 40
+    stz $00DF03
+    .endrept
+
+    .rept 40
+    stz $00DF03
+    .endrept
+
+    lda #$10
+    sta $00DF02
+    lda #$25
+    sta $00DF01
+    lda #$30
+    sta $00DF00
+
+    .rept 40
+    stz $00DF03
+    .endrept
+
+    .rept 40
+    lda #$55
+    sta $00DF03
+    .endrept
+    
+    lda #1 << 3
+    tsb SSCR
 
     .restore_registers
     rtl
@@ -23,16 +132,34 @@ vera_reset .proc
     lda #1 << 2
     trb PD4
 
-    ; Delay just a bit to make sure the reset takes effect.
-    ldx #10
-delay
+.block
+    ; Delay just a bit to make sure the FPGA is ready.
+    ldx #5
+delay_x
+    ldy #$FFFF
+delay_y
+    dey
+    bne delay_y
     dex
-    bne delay
+    bne delay_x
+.endblock
 
     ; Pull the VERA /RES line high
     lda #1 << 2
     tsb PD4
 
+.block
+    ; Delay just a bit to make sure the FPGA is ready.
+    ldx #30
+delay_x
+    ldy #$FFFF
+delay_y
+    dey
+    bne delay_y
+    dex
+    bne delay_x
+.endblock
+
     .restore_registers
     rtl
 .endproc