160 lines
3.2 KiB
OpenEdge ABL
160 lines
3.2 KiB
OpenEdge ABL
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AUTO_INC_NONE = $000000
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AUTO_INC_1 = $100000
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AUTO_INC_2 = $200000
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AUTO_INC_4 = $300000
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AUTO_INC_8 = $400000
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AUTO_INC_16 = $500000
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AUTO_INC_32 = $600000
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AUTO_INC_64 = $700000
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AUTO_INC_128 = $800000
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AUTO_INC_256 = $900000
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AUTO_INC_512 = $A00000
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AUTO_INC_40 = $B00000
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AUTO_INC_80 = $C00000
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AUTO_INC_160 = $D00000
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AUTO_INC_320 = $E00000
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AUTO_INC_640 = $F00000
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DISABLED = 0
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ENABLED = 1
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VERA_L_BPP1 = %00000000
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VERA_L_BPP2 = %00000001
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VERA_L_BPP4 = %00000010
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VERA_L_BPP8 = %00000011
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VERA_L_BITMAP = %00000100
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VERA_L_T256C = %00001000
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VERA_L_32W = %00000000
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VERA_L_64W = %00010000
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VERA_L_128W = %00100000
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VERA_L_256W = %00110000
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VERA_L_32H = %00000000
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VERA_L_64H = %01000000
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VERA_L_128H = %10000000
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VERA_L_256H = %11000000
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VERA_TILESIZE8x8 = %00000000
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VERA_TILESIZE16x8 = %00000001
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VERA_TILESIZE8x16 = %00000010
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VERA_TILESIZE16x16 = %00000011
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; The base address of the VERA chip
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VERA_BASE = $00DF00
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; Offsets (relative to VERA_BASE) for each VERA register
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VERA_ADDRx_L = VERA_BASE + 00
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VERA_ADDRx_M = VERA_BASE + 01
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VERA_ADDRx_H = VERA_BASE + 02
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; Accssible with ADDRSEL == 0
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VERA_ADDR0_L = VERA_BASE + 00
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VERA_ADDR0_M = VERA_BASE + 01
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VERA_ADDR0_H = VERA_BASE + 02
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; Accssible with ADDRSEL == 1
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VERA_ADDR1_L = VERA_BASE + 00
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VERA_ADDR1_M = VERA_BASE + 01
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VERA_ADDR1_H = VERA_BASE + 02
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VERA_DATA0 = VERA_BASE + $03
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VERA_DATA1 = VERA_BASE + $04
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VERA_CTRL = VERA_BASE + $05
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VERA_IEN = VERA_BASE + $06
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VERA_ISR = VERA_BASE + $06
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VERA_IRQLINE_L = VERA_BASE + $07
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VERA_SCANLINE_L = VERA_BASE + $08
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; Accssible with DCSEL == 0
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VERA_DC_VIDEO = VERA_BASE + $09
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VERA_DC_HSCALE = VERA_BASE + $0A
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VERA_DC_VSCALE = VERA_BASE + $0B
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VERA_DC_BORDER = VERA_BASE + $0C
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; Accssible with DCSEL == 1
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VERA_DC_HSTART = VERA_BASE + $09
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VERA_DC_HSTOP = VERA_BASE + $0A
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VERA_DC_VSTART = VERA_BASE + $0B
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VERA_DC_VSTOP = VERA_BASE + $0C
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; Layer 0
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VERA_L0_CONFIG = VERA_BASE + $0D
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VERA_L0_MAPBASE = VERA_BASE + $0E
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VERA_L0_TILEBASE = VERA_BASE + $0F
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VERA_L0_HSCROLL_L = VERA_BASE + $10
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VERA_L0_HSCROLL_H = VERA_BASE + $11
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VERA_L0_VSCROLL_L = VERA_BASE + $12
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VERA_L0_VSCROLL_H = VERA_BASE + $13
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; Layer 1
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VERA_L1_CONFIG = VERA_BASE + $14
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VERA_L1_MAPBASE = VERA_BASE + $15
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VERA_L1_TILEBASE = VERA_BASE + $16
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VERA_L1_HSCROLL_L = VERA_BASE + $17
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VERA_L1_HSCROLL_H = VERA_BASE + $18
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VERA_L1_VSCROLL_L = VERA_BASE + $19
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VERA_L1_VSCROLL_H = VERA_BASE + $1A
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; Audio
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VERA_AUDIO_CTRL = VERA_BASE + $1B
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VERA_AUDIO_RATE = VERA_BASE + $1C
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VERA_AUDIO_DATA = VERA_BASE + $1D
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; SPI (Unused in prototype four!)
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VERA_SPI_DATA = VERA_BASE + $1E
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VERA_SPI_CTRL = VERA_BASE + $1F
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; VRAM layout
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VERA_PSG_BASE = $1F9C0
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VERA_PALETTE_BASE = $1FA00
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VERA_SPRITE_ATTR_BASE = $1FC00
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; vpoke
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; writes an immediate byte to a given register
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vpoke .macro reg, value
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php
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rep #$20
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.al
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pha
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sep #$20
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.as
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lda #\value
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sta \reg
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rep #$20
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.al
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pla
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plp
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.endmacro
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; vera_address_set - sets the address registers to the passed in value
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vera_address_set .macro addr
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php
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rep #$20
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.al
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pha
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sep #$20
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.as
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lda #\addr & $ff
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sta VERA_ADDRx_L
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lda #(\addr >> 8) & $ff
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sta VERA_ADDRx_M
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lda #(\addr >> 16) & $ff
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sta VERA_ADDRx_H
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rep #$20
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.al
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pla
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plp
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.endmacro
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