Audio & Video

The VERA FPGA core, implemented on an iCE40 FPGA, is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the Commander X16 project by Frank van den Hoef, is licensed under the MIT license. It has been modified by Brian Swetland for Sentinel 65X, including porting it to be built using the Yosys open-source FPGA toolchain.

Video

The VERA video generator outputs a fixed 640x480, 60Hz digital RGB signal, with a total of 4,096 possible colours, using a 12-bit R4G4B4 colour space.

The video generation is done using two independent tile/bitmap layers, and a third layer composed of 128 sprites. VERA supports a single palette of 256 colours, freely chosen from the 4,096 possible colours available.

Audio

The VERA FPGA core produces audio output in i2S format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.

Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each chosen freely from among Pulse, Sawtooth, Triangle, and Noise.

VERA also generates sampled 48KHz 16-bit stereo audio from a 4KB on-chip memory buffer.

Interrupts

The VERA implementation in Sentinel 65X has a dedicated vectored interrupt line to the CPU, which can be triggered by any or all of four conditions: Sprite collision, line number, PCM buffer status, or VSYNC.

The Sentinel 65X A/V Port

Audio and video output in Sentinel 65X is directed to a pin header, which is connected to a small daughterboard which actually generates the final audio and video output signals, using electronics and connectors appropriate to the target display.

Pinout

The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:

Pin	Label	Label	Pin
1	+3.3V	+5V	2
3	HSYNC	VSYNC	4
5	RGB_R0	RGB_R1	6
7	RGB_R2	RGB_R3	8
9	RGB_G0	RGB_G1	10
11	RGB_G2	RGB_G3	12
13	RGB_B0	RGB_B1	14
15	RGB_B2	RGB_B3	16
17	LRCK	BCK	18
19	ADATA	SYSCLK	20
21	SCL	SDA	22
23	GND	GND	24

Hardware Registers

VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from 0x00DF00 to 0x00DF1F.

Addr	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
$00	ADDRx_L (x=ADDRSEL)	VRAM Address (7:0)
$01	ADDRx_M (x=ADDRSEL)	VRAM Address (15:8)
$02	ADDRx_H (x=ADDRSEL)	Address Increment				DECR	-		VRAM Address (16)
$03	DATA0	VRAM Data port 0
$04	DATA1	VRAM Data port 1
$05	CTRL	Reset	-					DCSEL	ADDRSEL
$06	IEN	IRQ Line (8)	Scan Line (8)	-		AFLOW	SPRCOL	LINE	VSYNC
$07	ISR	Sprite collissions				AFLOW	SPRCOL	LINE	VSYNC
$08	IRQLINE_L (Write only)	IRQ line (7:0)
$08	SCANLINE_L (Read only)	Scan line (7:0)
$09	DC_VIDEO (DCSEL=0)	Current Field	Sprites Enable	Layer1 Enable	Layer0 Enable	-	Chroma Disable	Output Mode
$0A	DC_HSCALE (DCSEL=0)	Active Display H-Scale
$0B	DC_VSCALE (DCSEL=0)	Active Display V-Scale
$0C	DC_BORDER (DCSEL=0)	Border Color
$09	DC_HSTART (DCSEL=1)	Active Display H-Start (9:2)
$0A	DC_HSTOP (DCSEL=1)	Active Display H-Stop (9:2)
$0B	DC_VSTART (DCSEL=1)	Active Display V-Start (8:1)
$0C	DC_VSTOP (DCSEL=1)	Active Display V-Stop (8:1)
$0D	L0_CONFIG	Map Height		Map Width		T256C	Bitmap Mode	Color Depth
$0E	L0_MAPBASE	Map Base Address (16:9)
$0F	L0_TILEBASE	Tile Base Address (16:11)						Tile Height	Tile Width
$10	L0_HSCROLL_L	H-Scroll (7:0)
$11	L0_HSCROLL_H	-				H-Scroll (11:8)
$12	L0_VSCROLL_L	V-Scroll (7:0)
$13	L0_VSCROLL_H	-				V-Scroll (11:8)
$14	L1_CONFIG	Map Height		Map Width		T256C	Bitmap Mode	Color Depth
$15	L1_MAPBASE	Map Base Address (16:9)
$16	L1_TILEBASE	Tile Base Address (16:11)						Tile Height	Tile Width
$17	L1_HSCROLL_L	H-Scroll (7:0)
$18	L1_HSCROLL_H	-				H-Scroll (11:8)
$19	L1_VSCROLL_L	V-Scroll (7:0)
$1A	L1_VSCROLL_H	-				V-Scroll (11:8)
$1B	AUDIO_CTRL	FIFO Full / FIFO Reset	FIFO Empty	16-Bit	Stereo	PCM Volume
$1C	AUDIO_RATE	PCM Sample Rate
$1D	AUDIO_DATA	Audio FIFO data (write-only)
$1E	SPI_DATA	Data
$1F	SPI_CTRL	Busy	-				Auto-tx	Slow clock	Select

VERA Memory

VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from 0x00000 to 0x1FFFF, and is organized as in the following table:

Address Range	Description
`0x00000` - `0x1F9BF`	Video RAM
`0x1F9C0` - `0x1F9FF`	Sound Registers
`0x1FA00` - `0x1FBFF`	Colour Palette
`0x1FC00` - `0x1FFFF`	Sprite Attributes

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