diff --git a/Audio & Video.md b/Audio & Video.md
index 025a79b..2e7faba 100644
--- a/Audio & Video.md	
+++ b/Audio & Video.md	
@@ -126,3 +126,39 @@ The `IEN` register, located at `0x00DF06`, has six bits which relate to the gene
 - Bit 3, called `IEN_AFLOW`, enables the interrupt triggered when the PCM sample buffer is less than 1/4 full.
 - Bit 6 contains the high-order bit of the 9-bit value of the `SCANLINE` register, located at `0x00DF08`. Both this bit and the `SCANLINE` register are read-only.
 - Bit 7 contains the high-order bit of the 9-bit value of the `IRQLINE` register, located at `0x00DF08`. Both this bit and the `IRQLINE` register are write-only.
+
+### ISR
+
+The `ISR` register, located at `0x00DF07`, contains flag bits which identify the source of the active VERA interrupt:
+
+- Bit 0, called `ISR_VSYNC`, identifies a VSYNC interrupt condition when set.
+- Bit 1, called `ISR_LINE`, identifies a raster line interrupt condition when set.
+- Bit 2, called `ISR_SPRCOL`, identifies a sprite collision interrupt condition when set.
+- Bit 3, called `ISR_AFLOW`, identifies a PCM sample buffer low interrupt condition when set.
+- Bits 4-7 store the sprite collision data.
+
+Writing a `1` value to bits 0, 1, or 2 will clear the interrupt state of the relevant interrupt source. Bit 3 can only be cleared by filling the PCM sample buffer to at least 1/4 of its capacity.
+
+### IRQLINE_L / SCANLINE_L
+
+The low order 8 bits of the current scanline and the scanline which is set to trigger the scanline interrupt share the address `0x00DF08` -- `IRQLINE_L` is write-only, and `SCANLINE_L` is read-only, so there is no conflict.
+
+### DC_VIDEO / DC_HSTART
+
+The `DC_Video` and `DC_HSTART` registers share the address `0x00DF09`; which one is accessed at that address is determined by the `DCSEL` flag bit in the [CTRL](#ctrl) register -- a `0` value in `DCSEL` will enable the `DC_VIDEO` register, and a `1` value the `DC_HSTART` register.
+
+`DC_VIDEO` stores three flag bits:
+
+- Bit 4 enables tile/bitmap layer 0 when set to `1`.
+- Bit 5 enables tile/bitmap layer 1 when set to `1`.
+- Bit 6 enables sprites when set to `1`.
+
+`DC_HSTART` controls the first active column of the screen, relative to the 640x480 display area. The value is the top 8 bits of a 10-bit number, the low order 2 bits of which are implied to be 0 -- that is, the value is an 8 bit number which will be multiplied by 4.
+
+### DC_HSCALE / DC_HSTOP
+
+The `DC_HSCALE` and `DC_HSTOP` registers share the address `0x00DF0A`; which one is accessed at that address is determined by the `DCSEL` flag bit in the [CTRL](#ctrl) register -- a `0` value in `DCSEL` will enable the `DC_HSCALE` register, and a `1` value the `DC_HSTOP` register.
+
+`DC_HSCALE` sets a fractional scaling factor of the active part of the screen; a value of 128 will output one pixel for each input pixel, and a value of 64 will output two pixels for each input pixel.
+
+`DC_HSTOP` controls the first active column of the screen, relative to the 640x480 display area. The value is the top 8 bits of a 10-bit number, the low order 2 bits of which are implied to be 0 -- that is, the value is an 8 bit number which will be multiplied by 4.