From ebd6b7ad207551d53287f6fd680714cc58593efb Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Fri, 22 Mar 2024 20:58:18 -0400 Subject: [PATCH] Work on fleshing out sections --- Clock Port.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Clock Port.md b/Clock Port.md index 5dc0479..29de891 100644 --- a/Clock Port.md +++ b/Clock Port.md @@ -7,6 +7,8 @@ include_toc: true The Sentinel 65X clock port is a small, 28-pin female pin header on the mainboard, which exposes the system's debug serial line, I2C bus, reset and main interrupt lines, `PHI2` clock signal, and a 64-address memory-mapped I/O region, mapped to memory beginning at `0x00DFC0`. This region of uncommitted expansion is reserved for the use of user-installed clock port accessories. +The clock port's pin header has two rows, and a pin and row pitch of 2.54mm. + ## Pinout The clock port's pinout, as seen from above, is shown in the following table: