From d33d61102d844b2cae7f086e30af1b2ab6b3318f Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sat, 23 Mar 2024 20:46:17 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 246 ----------------------------------------------- 1 file changed, 246 deletions(-) diff --git a/Audio & Video.md b/Audio & Video.md index 43642fe..103f921 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -52,252 +52,6 @@ The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
AddrNameBit 7Bit 6Bit 5 Bit 4Bit 3 Bit 2Bit 1 Bit 0
0x00DF00
ADDRx_L (x=ADDRSEL)VRAM Address (7:0)
`0x00DF01`ADDRx_M (x=ADDRSEL)VRAM Address (15:8)
`0x00DF02`ADDRx_H (x=ADDRSEL)Address IncrementDECR-VRAM Address (16)
`0x00DF03`DATA0VRAM Data port 0
$04DATA1VRAM Data port 1
$05CTRLReset-DCSELADDRSEL
$06IENIRQ Line (8)Scan Line (8)-AFLOWSPRCOLLINEVSYNC
$07ISRSprite collissionsAFLOWSPRCOLLINEVSYNC
$08IRQLINE_L (Write only)IRQ line (7:0)
$08SCANLINE_L (Read only)Scan line (7:0)
$09DC_VIDEO (DCSEL=0)Current FieldSprites EnableLayer1 EnableLayer0 Enable-Chroma DisableOutput Mode
$0ADC_HSCALE (DCSEL=0)Active Display H-Scale
$0BDC_VSCALE (DCSEL=0)Active Display V-Scale
$0CDC_BORDER (DCSEL=0)Border Color
$09DC_HSTART (DCSEL=1)Active Display H-Start (9:2)
$0ADC_HSTOP (DCSEL=1)Active Display H-Stop (9:2)
$0BDC_VSTART (DCSEL=1)Active Display V-Start (8:1)
$0CDC_VSTOP (DCSEL=1)Active Display V-Stop (8:1)
$0DL0_CONFIGMap HeightMap WidthT256CBitmap ModeColor Depth
$0EL0_MAPBASEMap Base Address (16:9)
$0FL0_TILEBASETile Base Address (16:11)Tile HeightTile Width
$10L0_HSCROLL_LH-Scroll (7:0)
$11L0_HSCROLL_H-H-Scroll (11:8)
$12L0_VSCROLL_LV-Scroll (7:0)
$13L0_VSCROLL_H-V-Scroll (11:8)
$14L1_CONFIGMap HeightMap WidthT256CBitmap ModeColor Depth
$15L1_MAPBASEMap Base Address (16:9)
$16L1_TILEBASETile Base Address (16:11)Tile HeightTile Width
$17L1_HSCROLL_LH-Scroll (7:0)
$18L1_HSCROLL_H-H-Scroll (11:8)
$19L1_VSCROLL_LV-Scroll (7:0)
$1AL1_VSCROLL_H-V-Scroll (11:8)
$1BAUDIO_CTRLFIFO Full / FIFO ResetFIFO Empty16-BitStereoPCM Volume
$1CAUDIO_RATEPCM Sample Rate
$1DAUDIO_DATAAudio FIFO data (write-only)
$1ESPI_DATAData
$1FSPI_CTRLBusy-Auto-txSlow clockSelect
- ## VERA Memory VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from `0x00000` to `0x1FFFF`, and is organized as in the following table: