Update Audio & Video.md
This commit is contained in:
parent
764f1f4242
commit
b022818c74
|
@ -23,7 +23,7 @@ There are enough sprites supported to act as a third bitmap layer, should the pr
|
||||||
|
|
||||||
## Audio
|
## Audio
|
||||||
|
|
||||||
The VERA FPGA core produces audio output in [I²S](https://en.wikipedia.org/wiki/I²S) format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.
|
The VERA FPGA core produces audio output in [I²S](https://en.wikipedia.org/wiki/I²S) format, which is fed to a compatible DAC to convert it to line-level analog stereo audio.
|
||||||
|
|
||||||
Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each chosen freely from among Pulse, Sawtooth, Triangle, and Noise.
|
Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each chosen freely from among Pulse, Sawtooth, Triangle, and Noise.
|
||||||
|
|
||||||
|
@ -33,28 +33,25 @@ VERA also generates sampled 48KHz 16-bit stereo audio from a 4KB on-chip memory
|
||||||
|
|
||||||
The VERA implementation in Sentinel 65X has a dedicated vectored interrupt line to the CPU, which can be triggered by any or all of four conditions: Sprite collision, line number, PCM buffer status, or VSYNC.
|
The VERA implementation in Sentinel 65X has a dedicated vectored interrupt line to the CPU, which can be triggered by any or all of four conditions: Sprite collision, line number, PCM buffer status, or VSYNC.
|
||||||
|
|
||||||
## The Sentinel 65X A/V Port
|
## The A/V Port
|
||||||
|
|
||||||
Audio and video output in Sentinel 65X is directed to a pin header, which is connected to a small daughterboard which actually generates the final audio and video output signals, using electronics and connectors appropriate to the target display.
|
Audio and video output in Sentinel 65X is also directed to a pin header, to which can be connected any accessory which might make productive use of the R, G, B, HSYNC, VSYNC, and L/R analog audio signals.
|
||||||
|
|
||||||
### Pinout
|
### Pinout
|
||||||
|
|
||||||
The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:
|
The A/V port is a 9-pin PTH footprint, with a pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:
|
||||||
|
|
||||||
| Pin | Label | | Label | Pin |
|
| Pin | Label |
|
||||||
| :---: | :-----: | --- | :----: | :---: |
|
| :---: | :-----: |
|
||||||
| 1 | +3.3V | | +5V | 2 |
|
| 1 | +5V |
|
||||||
| 3 | HSYNC | | VSYNC | 4 |
|
| 2 | AUDIO_R |
|
||||||
| 5 | RGB_R0 | | RGB_R1 | 6 |
|
| 3 | AUDIO_L |
|
||||||
| 7 | RGB_R2 | | RGB_R3 | 8 |
|
| 4 | VSYNC |
|
||||||
| 9 | RGB_G0 | | RGB_G1 | 10 |
|
| 5 | HSYNC |
|
||||||
| 11 | RGB_G2 | | RGB_G3 | 12 |
|
| 6 | RED |
|
||||||
| 13 | RGB_B0 | | RGB_B1 | 14 |
|
| 7 | GREEN |
|
||||||
| 15 | RGB_B2 | | RGB_B3 | 16 |
|
| 8 | BLUE |
|
||||||
| 17 | LRCK | | BCK | 18 |
|
| 9 | GND |
|
||||||
| 19 | ADATA | | SYSCLK | 20 |
|
|
||||||
| 21 | SCL | | SDA | 22 |
|
|
||||||
| 23 | GND | | GND | 24 |
|
|
||||||
|
|
||||||
## VERA Memory
|
## VERA Memory
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue