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Audio & Video.md
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The VERA FPGA core, implemented on an [iCE40 UltraPlus 5K FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys). The VERA FPGA core, implemented on an [iCE40 UltraPlus 5K FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys).
Note: This page contains documentation specific to the VERA as it is used in Sentinel 65X, and cannot be taken as applicable to any other project.
## Video ## Video
The VERA video generator outputs a fixed 640x480, 60Hz digital RGB signal, with a total of 4,096 possible colours, using a 12-bit R4G4B4 colour space. The VERA video generator outputs a fixed 640x480, 60Hz digital RGB signal, with a total of 4,096 possible colours, using a 12-bit R4G4B4 colour space.
@ -204,7 +206,7 @@ Bits 0-1 store the colour depth of the layer; that is, the number of bits used p
Bit 2 sets the layer to use tiles mode when set to `0`; a value of `1` will set the layer to use bitmap mode. Bit 2 sets the layer to use tiles mode when set to `0`; a value of `1` will set the layer to use bitmap mode.
Bit 3, called `T256C`, is used with tiles modes to enable or disable 256-colour 1bpp mode. Bit 3, called `T256C`, is used with tiles modes to enable or disable 256-colour 1bpp mode. Other tile mode colour depths ignore this flag bit.
Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, according to the values in the following table: Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, according to the values in the following table:
@ -394,7 +396,7 @@ Tilemaps are stored as sequences of two-byte structures. The interpretation of t
In 1bpp tile mode, with the `T256C` flag cleared, the first byte of the map data is an index into the tile data, and the second byte is split into two nybbles, the low-order nybble holding the foreground colour, and the high-order nybble holding the background colour for that tile. In 1bpp tile mode, with the `T256C` flag cleared, the first byte of the map data is an index into the tile data, and the second byte is split into two nybbles, the low-order nybble holding the foreground colour, and the high-order nybble holding the background colour for that tile.
In 1bpp tile mode with the `T256C` flag set, instead the second byte is the foreground colour of the tile, with the background colour being transparent. In 1bpp tile mode, with the `T256C` flag set, instead the second byte is the foreground colour of the tile, with the background colour being transparent.
### 2-, 4-, and 8-Bit Tile Modes ### 2-, 4-, and 8-Bit Tile Modes