Initial import
This commit is contained in:
Kyle Cardoza
parent
2e89072f5a
commit
633f4f80e7
|
|
@ -0,0 +1,2 @@
|
||||||
|
.DS_Store
|
||||||
|
|
||||||
|
|
@ -0,0 +1,83 @@
|
||||||
|
# Memory Management
|
||||||
|
|
||||||
|
Sentinel 65X, having a 65816-compatible CPU, has a 24-bit address bus, which allows for up to 16MB of linear address space. This space must contain all RAM, ROM, and I/O devices on the system, as the 65816 bus has no distinct notion of I/O addresses separate from memory addresses — it is a memory-mapped I/O architecture.
|
||||||
|
|
||||||
|
## Memory Regions
|
||||||
|
|
||||||
|
The 16MB address space of Sentinel 65X is divided into regions as follows:
|
||||||
|
|
||||||
|
- Region 0: 0x000000 to 0x0001FF 512 Bytes
|
||||||
|
- Region 1: 0x000200 to 0x007FFF 32,256 Bytes
|
||||||
|
- Region 2: 0x008000 to 0x00DEFF 24,320 Bytes
|
||||||
|
- Region 3: 0x00DF00 to 0x00DF1F 32 Bytes
|
||||||
|
- Region 4: 0x00DF20 to 0x00DFBF 160 Bytes
|
||||||
|
- Region 5: 0x00DFC0 to 0x00DFFF 64 Bytes
|
||||||
|
- Region 6: 0x00E000 to 0x00FFFF 8,192 Bytes
|
||||||
|
- Region 7: 0x010000 to 0x19FFFF 2,031,616 Bytes
|
||||||
|
- Region 8: 0x200000 to 0x3FFFFF 2,097,152 Bytes
|
||||||
|
- Region 9: 0x400000 to 0xBFFFFF 8,388,608 Bytes
|
||||||
|
- Region 10: 0xC00000 to 0xC7FFFF 524,288 Bytes
|
||||||
|
- Region 11: 0xC80000 to 0xFFFFFF 3,670,016 Bytes
|
||||||
|
|
||||||
|
Each of the above regions is configured separately:
|
||||||
|
|
||||||
|
- Region 0 is controlled by bit 2 of the system speed control register (SSCR) located at 0x00DF41. If that bit is clear, then region 0 selects the 512 byte SRAM on the CPU itself; if that bit is set, then region 0 selects the on-board 2MB SRAM chip.
|
||||||
|
- Region 1 selects the on-board 2MB SRAM chip as long as bit 5 of PCS7 (located at 0x00DF27) is set and bit 3 is clear; otherwise, it will select nothing.
|
||||||
|
- Region 2 is controlled by PCS7 as well; if bit 4 of PCS7 is set, then this region selects ROM; which ROM is selected in this case is controlled by the /CART signal on the expansion/cartridge connector. If /CART is high, then the on-board 512KB flash ROM will be selected; otherwise, the cartridge ROM connected to /ROM1 is selected instead.
|
||||||
|
- Region 3 is dedicated to the I/O space for the VERA chip.
|
||||||
|
- Region 4 is dedicated to on-CPU integrated peripheral devices.
|
||||||
|
- Region 5 is dedicated to the I/O space for the clock port.
|
||||||
|
- Region 6 is controlled by bit 7 of BCR, located at 0x00DF40. If that bit is clear, then the on-CPU mask ROM is selected. If that bit is set, then if bit 4 of PCS7 is set, then on-board flash ROM will be selected; otherwise, if bit 5 of PCS7 is set, then the on-board 2MB SRAM will be selected; otherwise, nothing will be selected.
|
||||||
|
- Region 7 is controlled by bit 5 of PCS7; if that bit is set, then the 2MB SRAM will be selected, otherwise nothing will be selected.
|
||||||
|
- Region 8 is also controlled by bit 5 of PCS7; if that bit is set, then the optional 2MB expansion RAM is selected, if present; otherwise, nothing is selected.
|
||||||
|
- Region 9 is controlled by bit 6 of PCS7; if that bit is set, then expansion space is selected. This region is dedicated to user expansions.
|
||||||
|
- Region 10 is controlled by bit 7 of PCS7. If that bit is set, then this region will select the on-board 512KB flash ROM. Otherwise, nothing will be selected.
|
||||||
|
- Region 11 is also controlled by bit 7 of PCS7. If that bit is set, then this region will select the expansion ROM, if installed. Otherwise, nothing will be selected. Note that if bits 4 and 7 of PCS7 are set, then the regions 0x008000 to 0x00DEFF and 0xC08000 to 0xC0DEFF will be mapped to the same area of ROM; if bit 7 of BCR is also set, then the regions 0x00E000 to 0x00FFFF and 0xC0E000 to 0xC0FFFF will also be mapped to the same physical memory.
|
||||||
|
Note that in the case that "nothing" is selected for a given address range, then user expansions are free to decode and make use of that address space for themselves.
|
||||||
|
|
||||||
|
In the case of memory regions 2 and 6, if bits 4 and 5 of PCS7 are both set, any attempt to select that region for reading will read the ROM, and any attemt to write to that region will write to the on-board SRAM.
|
||||||
|
|
||||||
|
## Main RAM
|
||||||
|
|
||||||
|
Sentinel 65X comes with 2MB of fast static RAM on the board. This memory is available in both 6502 emulation mode (in which only addresses from 0x0000 to 0xffff are valid) and in 65816 native mode.
|
||||||
|
|
||||||
|
## Main ROM
|
||||||
|
|
||||||
|
Sentinel 65X includes 512KB of rewritable flash ROM, on which is stored all built-in software for the system. Under normal operating conditions, with no cartridge or SD cards installed, the system is set up to boot the main ROM by default.
|
||||||
|
|
||||||
|
## Expansion RAM
|
||||||
|
|
||||||
|
Sentinel 65X supports expanding the RAM available to the system, using either or both of the cartridge and expansion ports. Expansion RAM can be mapped to any or all of memory regions 8, 9, and/or 11 without the use of any custom address decoding hardware, depending on the configuration of the expansion hardware.
|
||||||
|
|
||||||
|
## Expansion (Cartridge) ROM
|
||||||
|
|
||||||
|
Sentinel 65X supports additional ROM, located on cartridges. Cartridge ROM can be mapped to memory regions 2, 6, 8, 9, and 11, depending on the configuration of the expansion hardware.
|
||||||
|
|
||||||
|
## Updating ROM
|
||||||
|
|
||||||
|
Because Sentinel 65X uses paralle NOR flash ROM, it is fully possible to write directly to ROM using the standard flash write protocol; this is distinct from the simpler protocol to read ROM or read and write RAM. The system will eventually provide software which can update the ROM in offically-designed cartridges.
|
||||||
|
|
||||||
|
## Default Configuration
|
||||||
|
|
||||||
|
The kernel installed on the on-board flash ROM in Sentinel 65X will be designed to set up the following memory configuration:
|
||||||
|
|
||||||
|
- Region 0: On-CPU RAM
|
||||||
|
- Region 1: On-board RAM
|
||||||
|
- Region 2: On-board ROM
|
||||||
|
- Regions 3-5: I/O
|
||||||
|
- Region 6: On-board ROM
|
||||||
|
- Region 7: On-board RAM
|
||||||
|
- Region 8: Disabled
|
||||||
|
- Region 9: Disabled
|
||||||
|
- Region 10: On-board ROM
|
||||||
|
- Region 11: Disabled
|
||||||
|
|
||||||
|
This configuration is sufficient for most use cases, as all on-board hardware is enabled and set up to use. User software is, of course, free to reconfigure the memory map in any way needed.
|
||||||
|
|
||||||
|
## Cartridge and Expansion Memory
|
||||||
|
|
||||||
|
The Sentinel 65X cartridge port can accept cartridges with RAM, ROM, or memory-mapped I/O devices, mapping to the above-mentioned regions based on the specific pins of the cartridge port used to select the hardware on the cartridge. The expansion backplane, when installed, will allow the same behaviour with expansion cards.
|
||||||
|
|
||||||
|
By tying cartridge or expansion port pin b31, labeled /CART, to ground, a cartridge can be booted instead of the on-board flash ROM, as this will cause region 2 to be mapped to the /ROM1 pin on the cartridge connector. In this case, the cartridge ROM connected to the /ROM1 pin must have the ASCII value "WDC" beginning at offset 0x008000. If this is present, then ROM code will begin executing at offset 0x008004. It is usually advisable for the early boot code on a bootable ROM cartridge to set bit 4 of PCS7, which will map that same expansion ROM into region 6.
|
||||||
|
|
||||||
|
A cartridge or expansion which contains ROM does not necessarily need to be bootable, if it is intended as an accessory to software loaded from some other device.
|
||||||
Loading…
Reference in New Issue