From 59f58fdf3e6f86f419bbdd9ffd003c31398b2054 Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sat, 23 Mar 2024 21:11:33 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Audio & Video.md b/Audio & Video.md index 742d76e..7e2563b 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -65,20 +65,39 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe ### ADDRx_L -The `ADDRx_L` register is actually two registers, the `ADDR0_L` and `ADDR1_L` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. +The `ADDRx_L` register is actually two registers, the `ADDR0_L` and `ADDR1_L` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of `ADDRSEL`, which is bit 0 of the `CTRL` register, located at `0x00DF05`. The `ADDR0_L` and `ADDR1_L` registers control the low byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. ### ADDRx_M -The `ADDRx_M` register is actually two registers, the `ADDR0_M` and `ADDR1_M` registers. Which of the two is accessed at memory address `0x00DF01` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. +The `ADDRx_M` register is actually two registers, the `ADDR0_M` and `ADDR1_M` registers. Which of the two is accessed at memory address `0x00DF01` depends on the contents of `ADDRSEL`, which is bit 0 of the `CTRL` register, located at `0x00DF05`. The `ADDR0ML` and `ADDR1_M` registers control the middle byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. ### ADDRx_H -The `ADDRx_H` register is actually two registers, the `ADDR0_H` and `ADDR1_H` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. +The `ADDRx_H` register is actually two registers, the `ADDR0_H` and `ADDR1_H` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of `ADDRSEL`, which is bit 0 of the `CTRL` register, located at `0x00DF05`. The `ADDR0_H` and `ADDR1_H` registers control the low byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. -Bit 0 of the `ADDRx_H` is bit 16 of the address of the data port selected by `ADDRSEL`. Bits 1 and 2 of `ADDRx_H` are unused. Bit 3 is called `DECR`; when this bit is clear, the address of the selected data port will increment by the amount set with bits 4-7, according to the table below. When `DECR` is set, then the address will _decrement_ by the same amount. +Bit 0 of the `ADDRx_H` is bit 16 of the address of the data port selected by `ADDRSEL`. Bits 1 and 2 of `ADDRx_H` are unused. Bit 3 is called `DECR`; when this bit is clear, the address of the selected data port will increment by the amount set with bits 4-7, called `INCR`, according to the table below. When `DECR` is set, then the address will _decrement_ by the same amount. + +| `INCR` value | Address Increment | +| -------------: | ---------------: | +| 0 | 0 | +| 1 | 1 | +| 2 | 2 | +| 3 | 4 | +| 4 | 8 | +| 5 | 16 | +| 6 | 32 | +| 7 | 64 | +| 8 | 128 | +| 9 | 256 | +| 10 | 512 | +| 11 | 40 | +| 12 | 80 | +| 13 | 160 | +| 14 | 320 | +| 15 | 640 |