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Sentinel65X-Handbook
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Work on fleshing out sections

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Kyle Cardoza 2024-03-24 01:16:44 -04:00
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Audio & Video.md
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@ -227,15 +227,55 @@ The `L0_VSCROLL_L` and `L0_VSCROLL_H` registers, located at addresses `0x00DF12`
### Layer 1 Registers
The layer 1 control registers function exactly as their equivalents for layer 0:
The layer 1 control registers function exactly the same as their equivalents for layer 0:
- `L1_CONFIG` located at `0x00DF14`
- `L1_MAPBASE` located at `0x00DF15`
- `L1_TILEBASE` located at `0x00DF16`
- `L1_HSCROLL_L` located at `0x00DF17`
- `L1_HSCROLL_H` located at `0x00DF18`
- `L1_VSCROLL_L` located at `0x00DF19`
- `L1_VSCROLL_H` located at `0x00DF1A`
- `L1_CONFIG` is located at `0x00DF14`
- `L1_MAPBASE` is located at `0x00DF15`
- `L1_TILEBASE` is located at `0x00DF16`
- `L1_HSCROLL_L` is located at `0x00DF17`
- `L1_HSCROLL_H` is located at `0x00DF18`
- `L1_VSCROLL_L` is located at `0x00DF19`
- `L1_VSCROLL_H` is located at `0x00DF1A`
### AUDIO_CTRL
The `AUDIO_CTRL` register at `0x00DF1B` controls several aspects of the PCM audio subsystem:
- Bits 0-3 control the volume of the PCM sample playback.
- Bit 4 controls whether the PCM audio will be monaural (`0` value) or stereo (`1` value).
- Bit 5 controls whether PCM audio sample data is 8-bit (`0` value) or 16-bit (`1` value).
- Bit 6 is a read-only flag bit which indicates that the PCM sample buffer is empty when it is set to `1`.
- Bit 7 encodes two values; when read, this bit will be a `1` when the PCM sample buffer is full. In that case, writes to the buffer are silently ignored. When a `1` value is _written_ to this bit, the PCM sample buffer will be cleared.
### AUDIO_RATE
The `AUDIO_RATE` register at `0x00D1C` controls the sample rate of the PCM audio playback:
| Value | Description |
| :---: | :---------: |
| 128 | 48828.125Hz |
| 64 | 24414Hz |
| 32 | 12207Hz |
| 0 | No playback |
An intentional mismatch between the actual recorded sample rate and the sample rate of the playback can be used to speed up or slow down the PCM sample.
### AUDIO_DATA
The `AUDIO_DATA` register at `0x00DF1D` is a write-only register which accepts byte writes to the PCM audio buffer.
### SPI_DATA
The `SPI_DATA` register at `0x00DF1E` is used to read and write data from the selected SPI device a byte at a time.
### SPI_CTRL
The `SPI_CTRL` register at `0x00DF1F` is used to control the SPI subsystem:
- Bit 0 is used to assert the SPI select line with a `1` value, and deassert it with a `0` value.
- Bit 1 controls the clock rate of the SPI data clock; when set to `0` this will be approximately 12.5MHz, while when set to `1` the clock will run at approximately 390KHz, which can be useful with slow SPI devices or when an SD card requires a slower clock during initialization.
- Bit 2 controls the "auto-transmit" function, which begins reading a new byte from SPI (sending the value `0xFF`) automatically when the `SPI_DATA` register is read. This can be used to simplify and speed up SPI reads.
- Bit 7 will read as a `1` value as long as a byte is being transferred over SPI.
## 16-Bit Reads/Writes