Work on fleshing out sections
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@ -65,6 +65,8 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
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### ADDRx_L
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### ADDRx_L
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| `0x00DF00` | |
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<table>
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| :--------: | :---: |
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<tr>
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| VRAM Address (Low Byte ) ||
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<th>Address: <pre>0x00DF00</pre></th>
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</tr>
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</table>
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