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Sentinel65X-Handbook
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Work on fleshing out sections

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Kyle Cardoza 2024-03-23 20:45:49 -04:00
parent 4c5bc52ebb
commit 3a74d20880
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@ -66,7 +66,7 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
<th>Bit&nbsp;0</th> <th>Bit&nbsp;0</th>
</tr> </tr>
<tr> <tr>
<td>`0x00DF00`</td> <td><pre>0x00DF00</pre></td>
<td>ADDRx_L (x=ADDRSEL)</td> <td>ADDRx_L (x=ADDRSEL)</td>
<td colspan="8" align="center">VRAM Address (7:0)</td> <td colspan="8" align="center">VRAM Address (7:0)</td>
</tr> </tr>