diff --git a/Audio & Video.md b/Audio & Video.md
index 6a8d74b..025a79b 100644
--- a/Audio & Video.md	
+++ b/Audio & Video.md	
@@ -115,3 +115,14 @@ If the value in `INCR0` is nonzero, then after reading or writing from or to `DA
 ### CTRL
 
 The `CTRL` register, located at `0x00DF05`, contains three significant bits: bit 0, called `ADDRSEL`, determines which `DATAx` register the `ADDRx` registers refer to. Bit 1, called `DCSEL`, controls which set of registers are accessed at addresses `0x00DF09` through `0x00DF0C`. Bit 7, called `RESET`, will reset VERA to the initial power-on state when a `1` value is written to it.
+
+### IEN
+
+The `IEN` register, located at `0x00DF06`, has six bits which relate to the generation of VERA interrupts:
+
+- Bit 0, called `IEN_VSYNC`, enables the VSYNC interrupt when set.
+- Bit 1, called `IEN_LINE`, enables the raster-line interrupt when set.
+- Bit 2, called `IEN_SPRCOL`, enables the sprite collision interrupt when set.
+- Bit 3, called `IEN_AFLOW`, enables the interrupt triggered when the PCM sample buffer is less than 1/4 full.
+- Bit 6 contains the high-order bit of the 9-bit value of the `SCANLINE` register, located at `0x00DF08`. Both this bit and the `SCANLINE` register are read-only.
+- Bit 7 contains the high-order bit of the 9-bit value of the `IRQLINE` register, located at `0x00DF08`. Both this bit and the `IRQLINE` register are write-only.