From 295c714a0128208a80243b4ac42d27e4ae22f07d Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sat, 23 Mar 2024 21:08:29 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Audio & Video.md b/Audio & Video.md index 3a0b94c..742d76e 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -65,9 +65,20 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe ### ADDRx_L - - - - - -
Address: 0x00DF00ADDRx_L (x = ADDRSEL)
+The `ADDRx_L` register is actually two registers, the `ADDR0_L` and `ADDR1_L` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. + +The `ADDR0_L` and `ADDR1_L` registers control the low byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. + +### ADDRx_M + +The `ADDRx_M` register is actually two registers, the `ADDR0_M` and `ADDR1_M` registers. Which of the two is accessed at memory address `0x00DF01` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. + +The `ADDR0ML` and `ADDR1_M` registers control the middle byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. + +### ADDRx_H + +The `ADDRx_H` register is actually two registers, the `ADDR0_H` and `ADDR1_H` registers. Which of the two is accessed at memory address `0x00DF00` depends on the contents of ADDRSEL, which is bit 0 of the `CTRL` register, located at `0x00DF05`. + +The `ADDR0_H` and `ADDR1_H` registers control the low byte of the selected address in VERA memory for reading or writing with the `DATA0` and `DATA1` registers, located at `0x00DF03` and `0x00DF04` respectively. + +Bit 0 of the `ADDRx_H` is bit 16 of the address of the data port selected by `ADDRSEL`. Bits 1 and 2 of `ADDRx_H` are unused. Bit 3 is called `DECR`; when this bit is clear, the address of the selected data port will increment by the amount set with bits 4-7, according to the table below. When `DECR` is set, then the address will _decrement_ by the same amount.