From 1a91f03fc7d04989eff92c496f5058529f548207 Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sat, 23 Mar 2024 20:50:14 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Audio & Video.md b/Audio & Video.md index 103f921..779fb2b 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -48,10 +48,6 @@ The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. | 21 | SCL | | SDA | 22 | | 23 | GND | | GND | 24 | -## Hardware Registers - -VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`. - ## VERA Memory VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from `0x00000` to `0x1FFFF`, and is organized as in the following table: @@ -62,3 +58,13 @@ VERA implements 128KB of internal memory, which exists in its own independent ad | `0x1F9C0` - `0x1F9FF` | Sound Registers | | `0x1FA00` - `0x1FBFF` | Colour Palette | | `0x1FC00` - `0x1FFFF` | Sprite Attributes | + +## Hardware Registers + +VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`. + +### ADDRx_L + +| `0x00DF00` | || +| :--------: | :---: || +| VRAM Address (Low Byte ) ||