65X-DOS/include/kernel/hardware/w65c265s.h

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// SPDX-License-Identifier: MIT
//
// boot/w65c265s.h
// Defines for the W65C265S chip
//
// Copyright © 2024 Kyle J Cardoza <Kyle.Cardoza@icloud.com>
#define PD0 0x00DF00
#define PD1 0x00DF01
#define PD2 0x00DF02
#define PD3 0x00DF03
#define PD4 0x00DF20
#define PD5 0x00DF21
#define PD6 0x00DF22
#define PD7 0x00DF23
#define PDD0 0x00DF04
#define PDD1 0x00DF05
#define PDD2 0x00DF06
#define PDD3 0x00DF07
#define PDD4 0x00DF24
#define PDD5 0x00DF25
#define PDD6 0x00DF26
#define PCS7 0x00DF27
#define BCR 0x00DF40
#define SSCR 0x00DF41
#define TCR 0x00DF42
#define TER 0x00DF43
#define TIFR 0x00DF44
#define EIFR 0x00DF45
#define TIER 0x00DF46
#define EIER 0x00DF47
#define UIFR 0x00DF48
#define UIER 0x00DF49
#define T0LL 0x00DF50
#define T0LH 0x00DF51
#define T1LL 0x00DF52
#define T1LH 0x00DF53
#define T2LL 0x00DF54
#define T2LH 0x00DF55
#define T3LL 0x00DF56
#define T3LH 0x00DF57
#define T4LL 0x00DF58
#define T4LH 0x00DF59
#define T5LL 0x00DF5A
#define T5LH 0x00DF5B
#define T6LL 0x00DF5C
#define T6LH 0x00DF5D
#define T7LL 0x00DF5E
#define T7LH 0x00DF5F
#define T0CL 0x00DF60
#define T0CH 0x00DF61
#define T1CL 0x00DF62
#define T1CH 0x00DF63
#define T2CL 0x00DF64
#define T2CH 0x00DF65
#define T3CL 0x00DF66
#define T3CH 0x00DF67
#define T4CL 0x00DF68
#define T4CH 0x00DF69
#define T5CL 0x00DF6A
#define T5CH 0x00DF6B
#define T6CL 0x00DF6C
#define T6CH 0x00DF6D
#define T7CL 0x00DF6E
#define T7CH 0x00DF6F
#define ACSR0 0x00DF70
#define ARTD0 0x00DF71
#define ACSR1 0x00DF72
#define ARTD1 0x00DF73
#define ACSR2 0x00DF74
#define ARTD2 0x00DF75
#define ACSR3 0x00DF76
#define ARTD3 0x00DF77
#define PIBFR 0x00DF78
#define PIBER 0x00DF79
#define PIR2 0x00DF7A
#define PIR3 0x00DF7B
#define PIR4 0x00DF7C
#define PIR5 0x00DF7D
#define PIR6 0x00DF7E
#define PIR7 0x00DF7F
#ifdef __CALYPSI_ASSEMBLER__
; Enable the 512 bytes of on-CPU SRAM from 0x000000-0001FF
w65c265s_sram_on .macro
lda #0b00000100
trb SSCR
.endm
w65c265s_sram_off .macro
lda #0b00000100
tsb SSCR
.endm
; Disable the on-CPU ROM
w65c265s_rom_off .macro
lda #1 << 7
tsb BCR
.endm
; Enable the on-CPU ROM
w65c265s_rom_on .macro
lda #1 << 7
trb BCR
.endm
; Start FCLK
fclk_start .macro
lda #0b00000001
tsb SSCR
.endm
; Stop FCLK
fclk_stop .macro
lda #0b00000001
trb SSCR
.endm
; Select FCLK as the clock source
fclk_select .macro
lda #0b11111010
tsb SSCR
.endm
#endif