472 lines
13 KiB
ArmAsm
472 lines
13 KiB
ArmAsm
; Generated by Calypsi ISO C compiler for 65816
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.rtmodel version,"1"
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.rtmodel codeModel,"large"
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.rtmodel dataModel,"small"
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.rtmodel core,"65816"
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.rtmodel huge,"0"
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.extern _Dp
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.extern _Vfp
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.extern vera_addr_h_write
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.extern vera_addr_l_write
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.extern vera_addr_m_write
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.extern vera_ctrl_read
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.extern vera_ctrl_write
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.extern vera_data_0_read
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.extern vera_data_0_write
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.extern vera_dc_hscale_write
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.extern vera_dc_hstart_write
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.extern vera_dc_hstop_write
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.extern vera_dc_video_write
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.extern vera_dc_vscale_write
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.extern vera_dc_vstart_write
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.extern vera_dc_vstop_write
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.extern vera_font_0
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.extern vera_ien_write
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.extern vera_isr_write
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.extern vera_l0_config_write
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.extern vera_l0_hscroll_h_write
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.extern vera_l0_hscroll_l_write
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.extern vera_l0_mapbase_write
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.extern vera_l0_tilebase_write
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.extern vera_l0_vscroll_h_write
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.extern vera_l0_vscroll_l_write
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.extern vera_palette
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; // SPDX-License-Identifier: MIT
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; //
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; // src/kernel/hardware/vera/vera.c
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; // IRQ handlers
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; //
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; // Copyright © 2024 Kyle J Cardoza <Kyle.Cardoza@icloud.com>
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;
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; #include <stdint.h>
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;
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; #include "kernel/hardware/vera.h"
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; #include "kernel/util/delay.h"
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;
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; extern uint16_t *vera_palette;
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;
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; extern uint8_t *vera_font_0;
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;
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; void vera_address_select(uint8_t value) {
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.section farcode,text
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.public vera_address_select
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vera_address_select:
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phy
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sep #32
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sta 1,s
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rep #32
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; uint8_t ctrl = vera_ctrl_read();
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jsl long:vera_ctrl_read
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sep #32
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sta 2,s
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rep #32
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;
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; if (value == 0) {
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sep #32
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lda 1,s
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rep #32
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bne `?L4`
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; ctrl &= 0b11111110;
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lda ##254
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and 2,s
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sep #32
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sta 1,s
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rep #32
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sep #32
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lda 1,s
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sta 1,s
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rep #32
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bra `?L5`
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`?L4`:
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; } else {
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; ctrl |= 0b00000001;
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lda ##1
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ora 2,s
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sep #32
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sta 1,s
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rep #32
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sep #32
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lda 1,s
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sta 1,s
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rep #32
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`?L5`:
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; }
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;
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; vera_ctrl_write(ctrl);
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lda 1,s
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jsl long:vera_ctrl_write
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; }
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ply
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rtl
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;
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; void vera_address_set(uint32_t address) {
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.section farcode,text
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.public vera_address_set
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vera_address_set:
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pei dp:.tiny (_Dp+8)
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pei dp:.tiny (_Dp+10)
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stx dp:.tiny (_Dp+10)
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sta dp:.tiny (_Dp+8)
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; vera_addr_l_write(address & 0x000000FF);
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lda dp:.tiny (_Dp+8)
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jsl long:vera_addr_l_write
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; vera_addr_m_write((address >> 8) & 0x000000FF);
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ldx dp:.tiny (_Dp+10)
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lda dp:.tiny (_Dp+8)
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ldy ##8
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stx dp:.tiny _Dp
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iny
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dey
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beq `?L47`
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`?L48`:
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lsr dp:.tiny _Dp
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ror a
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dey
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bne `?L48`
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`?L47`:
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ldx dp:.tiny _Dp
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stx dp:.tiny (_Dp+2)
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sta dp:.tiny _Dp
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lda dp:.tiny (_Dp+2)
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and ##0
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tax
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lda dp:.tiny _Dp
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and ##255
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jsl long:vera_addr_m_write
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; vera_addr_h_write((address >> 16) & 0x000000FF);
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ldx dp:.tiny (_Dp+10)
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lda dp:.tiny (_Dp+8)
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txa
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ldx ##0
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stx dp:.tiny (_Dp+2)
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sta dp:.tiny _Dp
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lda dp:.tiny (_Dp+2)
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and ##0
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tax
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lda dp:.tiny _Dp
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and ##255
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jsl long:vera_addr_h_write
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; }
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ply
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sty dp:.tiny (_Dp+10)
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ply
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sty dp:.tiny (_Dp+8)
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rtl
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;
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; void vera_mem_read(void *dest, uint32_t src, size_t length) {
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.section farcode,text
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.public vera_mem_read
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vera_mem_read:
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pei dp:.tiny (_Dp+8)
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pei dp:.tiny (_Dp+10)
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phy
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phy
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ldx dp:.tiny _Dp
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stx dp:.tiny (_Dp+8)
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ldx dp:.tiny (_Dp+2)
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stx dp:.tiny (_Dp+10)
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; uint8_t *destination = dest;
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sta 1,s
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;
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; vera_address_select(0);
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lda ##0
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jsl long:vera_address_select
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; vera_address_set(src | AUTO_INC_1);
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lda dp:.tiny (_Dp+10)
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ora ##16
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tax
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lda dp:.tiny (_Dp+8)
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ora ##0
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jsl long:vera_address_set
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;
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; for (size_t count = 0; count < length; count += 1) {
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lda ##0
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sta 3,s
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lda 3,s
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sta 3,s
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`?L14`: lda 3,s
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cmp 12,s
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bcc `?L13`
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; destination[count] = vera_data_0_read();
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; }
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; }
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ply
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ply
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ply
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sty dp:.tiny (_Dp+10)
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ply
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sty dp:.tiny (_Dp+8)
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rtl
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`?L13`:
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jsl long:vera_data_0_read
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tax
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lda 1,s
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tay
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txa
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sep #32
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sta (3,s),y
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rep #32
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lda 3,s
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inc a
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sta 3,s
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bra `?L14`
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;
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; void vera_mem_write(uint32_t dest, void *src, size_t length) {
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.section farcode,text
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.public vera_mem_write
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vera_mem_write:
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pei dp:.tiny (_Dp+8)
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pei dp:.tiny (_Dp+10)
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pei dp:.tiny (_Dp+12)
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pei dp:.tiny (_Dp+14)
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phy
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phy
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stx dp:.tiny (_Dp+14)
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sta dp:.tiny (_Dp+12)
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lda dp:.tiny _Dp
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sta dp:.tiny (_Dp+10)
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lda dp:.tiny (_Dp+2)
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sta dp:.tiny (_Dp+8)
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; vera_address_select(0);
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lda ##0
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jsl long:vera_address_select
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; vera_address_set(dest | AUTO_INC_1);
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lda dp:.tiny (_Dp+14)
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ora ##16
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tax
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lda dp:.tiny (_Dp+12)
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ora ##0
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jsl long:vera_address_set
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;
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; uint8_t *source = src;
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lda dp:.tiny (_Dp+10)
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sta 1,s
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;
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; for (size_t count = 0; count < length; count += 1) {
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lda ##0
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sta 3,s
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lda 3,s
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sta 3,s
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`?L21`: lda 3,s
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cmp dp:.tiny (_Dp+8)
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bcc `?L20`
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; vera_data_0_write(source[count]);
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; }
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; }
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ply
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ply
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ply
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sty dp:.tiny (_Dp+14)
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ply
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sty dp:.tiny (_Dp+12)
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ply
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sty dp:.tiny (_Dp+10)
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ply
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sty dp:.tiny (_Dp+8)
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rtl
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`?L20`: lda 1,s
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tay
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lda (3,s),y
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jsl long:vera_data_0_write
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lda 3,s
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inc a
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sta 3,s
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bra `?L21`
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;
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; void vera_mem_set(uint32_t dest, uint8_t value, size_t length) {
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.section farcode,text
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.public vera_mem_set
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vera_mem_set:
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pei dp:.tiny (_Dp+8)
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pei dp:.tiny (_Dp+12)
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pei dp:.tiny (_Dp+14)
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phy
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stx dp:.tiny (_Dp+14)
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sta dp:.tiny (_Dp+12)
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lda dp:.tiny _Dp
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sta dp:.tiny (_Dp+8)
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; vera_address_select(0);
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lda ##0
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jsl long:vera_address_select
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; vera_address_set(dest | AUTO_INC_1);
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lda dp:.tiny (_Dp+14)
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ora ##16
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tax
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lda dp:.tiny (_Dp+12)
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ora ##0
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jsl long:vera_address_set
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;
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; for (size_t count = 0; count < length; count += 1) {
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lda ##0
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sta 1,s
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lda 1,s
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sta 1,s
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`?L28`: lda 1,s
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cmp dp:.tiny (_Dp+8)
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bcc `?L27`
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; vera_data_0_write(value);
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; }
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; }
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ply
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ply
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sty dp:.tiny (_Dp+14)
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ply
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sty dp:.tiny (_Dp+12)
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ply
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sty dp:.tiny (_Dp+8)
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rtl
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`?L27`: lda 12,s
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jsl long:vera_data_0_write
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lda 1,s
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inc a
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sta 1,s
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bra `?L28`
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;
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; void vera_mem_clear(uint32_t dest, size_t length) {
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.section farcode,text
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.public vera_mem_clear
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vera_mem_clear:
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pei dp:.tiny (_Dp+8)
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pei dp:.tiny (_Dp+12)
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pei dp:.tiny (_Dp+14)
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phy
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stx dp:.tiny (_Dp+14)
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sta dp:.tiny (_Dp+12)
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lda dp:.tiny _Dp
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sta dp:.tiny (_Dp+8)
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; vera_address_select(0);
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lda ##0
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jsl long:vera_address_select
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; vera_address_set(dest | AUTO_INC_1);
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lda dp:.tiny (_Dp+14)
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ora ##16
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tax
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lda dp:.tiny (_Dp+12)
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ora ##0
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jsl long:vera_address_set
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;
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; for (size_t count = 0; count < length; count += 1) {
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lda ##0
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sta 1,s
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lda 1,s
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sta 1,s
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`?L35`: lda 1,s
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cmp dp:.tiny (_Dp+8)
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bcc `?L34`
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; vera_data_0_write(0x00);
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; }
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; }
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ply
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ply
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sty dp:.tiny (_Dp+14)
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ply
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sty dp:.tiny (_Dp+12)
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ply
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sty dp:.tiny (_Dp+8)
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rtl
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`?L34`: lda ##0
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jsl long:vera_data_0_write
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lda 1,s
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inc a
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sta 1,s
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bra `?L35`
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;
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; void vera_reset(void) {
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.section farcode,text
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.public vera_reset
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vera_reset:
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; uint8_t ctrl = vera_ctrl_read();
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jsl long:vera_ctrl_read
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; vera_ctrl_write(ctrl | (1 << 7));
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ora ##128
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jsl long:vera_ctrl_write
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; }
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rtl
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;
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; void vera_init(void) {
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.section farcode,text
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.public vera_init
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vera_init:
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;
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; vera_mem_write(VERA_PALETTE_BASE, vera_palette, 0x200);
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ldx ##0x200
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stx dp:.tiny (_Dp+2)
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ldx vera_palette
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stx dp:.tiny _Dp
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lda ##0xfa00
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ldx ##1
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jsl long:vera_mem_write
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; vera_mem_write(TEXT_CONSOLE_TILES, vera_font_0, 0x1000);
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ldx ##0x1000
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stx dp:.tiny (_Dp+2)
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ldx vera_font_0
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stx dp:.tiny _Dp
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lda ##0x800
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ldx ##0
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jsl long:vera_mem_write
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;
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; vera_dc_hscale_write(0x80);
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lda ##128
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jsl long:vera_dc_hscale_write
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; vera_dc_vscale_write(0x80);
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lda ##128
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jsl long:vera_dc_vscale_write
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;
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; vera_dc_hstart_write(0);
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lda ##0
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jsl long:vera_dc_hstart_write
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; vera_dc_hstop_write(640 >> 2);
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lda ##160
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jsl long:vera_dc_hstop_write
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; vera_dc_vstart_write(0);
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lda ##0
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jsl long:vera_dc_vstart_write
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; vera_dc_vstop_write(480 >> 1);
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lda ##240
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jsl long:vera_dc_vstop_write
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;
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; vera_l0_config_write(VERA_L_BPP1 | VERA_L_64H | VERA_L_128W);
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lda ##96
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jsl long:vera_l0_config_write
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; vera_l0_mapbase_write(TEXT_CONSOLE0_VRAM >> 9);
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lda ##12
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jsl long:vera_l0_mapbase_write
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; vera_l0_tilebase_write(((TEXT_CONSOLE_TILES >> 9) & 0b11111100) | VERA_TILESIZE8x16);
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lda ##6
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jsl long:vera_l0_tilebase_write
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; vera_l0_hscroll_l_write(0);
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lda ##0
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jsl long:vera_l0_hscroll_l_write
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; vera_l0_hscroll_h_write(0);
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lda ##0
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jsl long:vera_l0_hscroll_h_write
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; vera_l0_vscroll_l_write(0);
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lda ##0
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jsl long:vera_l0_vscroll_l_write
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; vera_l0_vscroll_h_write(0);
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lda ##0
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jsl long:vera_l0_vscroll_h_write
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;
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; vera_ien_write(0b00000000);
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lda ##0
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jsl long:vera_ien_write
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; vera_isr_write(0b00000111);
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lda ##7
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jsl long:vera_isr_write
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; vera_dc_video_write(0b00010001);
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lda ##17
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jsl long:vera_dc_video_write
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;
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; vera_mem_write(TEXT_CONSOLE0_VRAM, (void*)(0xC00000), 0x4000);
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ldx ##0x4000
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stx dp:.tiny (_Dp+2)
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ldx ##0
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stx dp:.tiny _Dp
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lda ##0x1800
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ldx ##0
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jsl long:vera_mem_write
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; }
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rtl
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