; Generated by Calypsi ISO C compiler for 65816

            .rtmodel version,"1"
            .rtmodel codeModel,"large"
            .rtmodel dataModel,"small"
            .rtmodel core,"65816"
            .rtmodel huge,"0"
            .extern _Dp
            .extern _Vfp
            .extern vera_addr_h_write
            .extern vera_addr_l_write
            .extern vera_addr_m_write
            .extern vera_ctrl_read
            .extern vera_ctrl_write
            .extern vera_data_0_read
            .extern vera_data_0_write
            .extern vera_dc_hscale_write
            .extern vera_dc_hstart_write
            .extern vera_dc_hstop_write
            .extern vera_dc_video_write
            .extern vera_dc_vscale_write
            .extern vera_dc_vstart_write
            .extern vera_dc_vstop_write
            .extern vera_font_0
            .extern vera_ien_write
            .extern vera_isr_write
            .extern vera_l0_config_write
            .extern vera_l0_hscroll_h_write
            .extern vera_l0_hscroll_l_write
            .extern vera_l0_mapbase_write
            .extern vera_l0_tilebase_write
            .extern vera_l0_vscroll_h_write
            .extern vera_l0_vscroll_l_write
            .extern vera_palette
;  // SPDX-License-Identifier: MIT
;  //
;  // src/kernel/hardware/vera/vera.c
;  //      IRQ handlers
;  //
;  // Copyright © 2024 Kyle J Cardoza <Kyle.Cardoza@icloud.com>
;
;  #include <stdint.h>
;
;  #include "kernel/hardware/vera.h"
;  #include "kernel/util/delay.h"
;
;  extern uint16_t *vera_palette;
;
;  extern uint8_t *vera_font_0;
;
;  void vera_address_select(uint8_t value) {
            .section farcode,text
            .public vera_address_select
vera_address_select:
            phy
            sep     #32
            sta     1,s
            rep     #32
;  	uint8_t ctrl = vera_ctrl_read();
            jsl     long:vera_ctrl_read
            sep     #32
            sta     2,s
            rep     #32
;
;  	if (value == 0) {
            sep     #32
            lda     1,s
            rep     #32
            bne     `?L4`
;  		ctrl &= 0b11111110;
            lda     ##254
            and     2,s
            sep     #32
            sta     1,s
            rep     #32
            sep     #32
            lda     1,s
            sta     1,s
            rep     #32
            bra     `?L5`
`?L4`:
;  	} else {
;  		ctrl |= 0b00000001;
            lda     ##1
            ora     2,s
            sep     #32
            sta     1,s
            rep     #32
            sep     #32
            lda     1,s
            sta     1,s
            rep     #32
`?L5`:
;  	}
;
;  	vera_ctrl_write(ctrl);
            lda     1,s
            jsl     long:vera_ctrl_write
;  }
            ply
            rtl
;
;  void vera_address_set(uint32_t address) {
            .section farcode,text
            .public vera_address_set
vera_address_set:
            pei     dp:.tiny (_Dp+8)
            pei     dp:.tiny (_Dp+10)
            stx     dp:.tiny (_Dp+10)
            sta     dp:.tiny (_Dp+8)
;  	vera_addr_l_write(address & 0x000000FF);
            lda     dp:.tiny (_Dp+8)
            jsl     long:vera_addr_l_write
;  	vera_addr_m_write((address >> 8) & 0x000000FF);
            ldx     dp:.tiny (_Dp+10)
            lda     dp:.tiny (_Dp+8)
            ldy     ##8
            stx     dp:.tiny _Dp
            iny
            dey
            beq     `?L47`
`?L48`:
            lsr     dp:.tiny _Dp
            ror     a
            dey
            bne     `?L48`
`?L47`:
            ldx     dp:.tiny _Dp
            stx     dp:.tiny (_Dp+2)
            sta     dp:.tiny _Dp
            lda     dp:.tiny (_Dp+2)
            and     ##0
            tax
            lda     dp:.tiny _Dp
            and     ##255
            jsl     long:vera_addr_m_write
;  	vera_addr_h_write((address >> 16) & 0x000000FF);
            ldx     dp:.tiny (_Dp+10)
            lda     dp:.tiny (_Dp+8)
            txa
            ldx     ##0
            stx     dp:.tiny (_Dp+2)
            sta     dp:.tiny _Dp
            lda     dp:.tiny (_Dp+2)
            and     ##0
            tax
            lda     dp:.tiny _Dp
            and     ##255
            jsl     long:vera_addr_h_write
;  }
            ply
            sty     dp:.tiny (_Dp+10)
            ply
            sty     dp:.tiny (_Dp+8)
            rtl
;
;  void vera_mem_read(void *dest, uint32_t src, size_t length) {
            .section farcode,text
            .public vera_mem_read
vera_mem_read:
            pei     dp:.tiny (_Dp+8)
            pei     dp:.tiny (_Dp+10)
            phy
            phy
            ldx     dp:.tiny _Dp
            stx     dp:.tiny (_Dp+8)
            ldx     dp:.tiny (_Dp+2)
            stx     dp:.tiny (_Dp+10)
;  	uint8_t *destination = dest;
            sta     1,s
;
;  	vera_address_select(0);
            lda     ##0
            jsl     long:vera_address_select
;  	vera_address_set(src | AUTO_INC_1);
            lda     dp:.tiny (_Dp+10)
            ora     ##16
            tax
            lda     dp:.tiny (_Dp+8)
            ora     ##0
            jsl     long:vera_address_set
;
;  	for (size_t count = 0; count < length; count += 1) {
            lda     ##0
            sta     3,s
            lda     3,s
            sta     3,s
`?L14`:     lda     3,s
            cmp     12,s
            bcc     `?L13`
;  		destination[count] = vera_data_0_read();
;  	}
;  }
            ply
            ply
            ply
            sty     dp:.tiny (_Dp+10)
            ply
            sty     dp:.tiny (_Dp+8)
            rtl
`?L13`:
            jsl     long:vera_data_0_read
            tax
            lda     1,s
            tay
            txa
            sep     #32
            sta     (3,s),y
            rep     #32
            lda     3,s
            inc     a
            sta     3,s
            bra     `?L14`
;
;  void vera_mem_write(uint32_t dest, void *src, size_t length) {
            .section farcode,text
            .public vera_mem_write
vera_mem_write:
            pei     dp:.tiny (_Dp+8)
            pei     dp:.tiny (_Dp+10)
            pei     dp:.tiny (_Dp+12)
            pei     dp:.tiny (_Dp+14)
            phy
            phy
            stx     dp:.tiny (_Dp+14)
            sta     dp:.tiny (_Dp+12)
            lda     dp:.tiny _Dp
            sta     dp:.tiny (_Dp+10)
            lda     dp:.tiny (_Dp+2)
            sta     dp:.tiny (_Dp+8)
;  	vera_address_select(0);
            lda     ##0
            jsl     long:vera_address_select
;  	vera_address_set(dest | AUTO_INC_1);
            lda     dp:.tiny (_Dp+14)
            ora     ##16
            tax
            lda     dp:.tiny (_Dp+12)
            ora     ##0
            jsl     long:vera_address_set
;
;  	uint8_t *source = src;
            lda     dp:.tiny (_Dp+10)
            sta     1,s
;
;  	for (size_t count = 0; count < length; count += 1) {
            lda     ##0
            sta     3,s
            lda     3,s
            sta     3,s
`?L21`:     lda     3,s
            cmp     dp:.tiny (_Dp+8)
            bcc     `?L20`
;  		vera_data_0_write(source[count]);
;  	}
;  }
            ply
            ply
            ply
            sty     dp:.tiny (_Dp+14)
            ply
            sty     dp:.tiny (_Dp+12)
            ply
            sty     dp:.tiny (_Dp+10)
            ply
            sty     dp:.tiny (_Dp+8)
            rtl
`?L20`:     lda     1,s
            tay
            lda     (3,s),y
            jsl     long:vera_data_0_write
            lda     3,s
            inc     a
            sta     3,s
            bra     `?L21`
;
;  void vera_mem_set(uint32_t dest, uint8_t value, size_t length) {
            .section farcode,text
            .public vera_mem_set
vera_mem_set:
            pei     dp:.tiny (_Dp+8)
            pei     dp:.tiny (_Dp+12)
            pei     dp:.tiny (_Dp+14)
            phy
            stx     dp:.tiny (_Dp+14)
            sta     dp:.tiny (_Dp+12)
            lda     dp:.tiny _Dp
            sta     dp:.tiny (_Dp+8)
;  	vera_address_select(0);
            lda     ##0
            jsl     long:vera_address_select
;  	vera_address_set(dest | AUTO_INC_1);
            lda     dp:.tiny (_Dp+14)
            ora     ##16
            tax
            lda     dp:.tiny (_Dp+12)
            ora     ##0
            jsl     long:vera_address_set
;
;  	for (size_t count = 0; count < length; count += 1) {
            lda     ##0
            sta     1,s
            lda     1,s
            sta     1,s
`?L28`:     lda     1,s
            cmp     dp:.tiny (_Dp+8)
            bcc     `?L27`
;  		vera_data_0_write(value);
;  	}
;  }
            ply
            ply
            sty     dp:.tiny (_Dp+14)
            ply
            sty     dp:.tiny (_Dp+12)
            ply
            sty     dp:.tiny (_Dp+8)
            rtl
`?L27`:     lda     12,s
            jsl     long:vera_data_0_write
            lda     1,s
            inc     a
            sta     1,s
            bra     `?L28`
;
;  void vera_mem_clear(uint32_t dest, size_t length) {
            .section farcode,text
            .public vera_mem_clear
vera_mem_clear:
            pei     dp:.tiny (_Dp+8)
            pei     dp:.tiny (_Dp+12)
            pei     dp:.tiny (_Dp+14)
            phy
            stx     dp:.tiny (_Dp+14)
            sta     dp:.tiny (_Dp+12)
            lda     dp:.tiny _Dp
            sta     dp:.tiny (_Dp+8)
;  	vera_address_select(0);
            lda     ##0
            jsl     long:vera_address_select
;  	vera_address_set(dest | AUTO_INC_1);
            lda     dp:.tiny (_Dp+14)
            ora     ##16
            tax
            lda     dp:.tiny (_Dp+12)
            ora     ##0
            jsl     long:vera_address_set
;
;  	for (size_t count = 0; count < length; count += 1) {
            lda     ##0
            sta     1,s
            lda     1,s
            sta     1,s
`?L35`:     lda     1,s
            cmp     dp:.tiny (_Dp+8)
            bcc     `?L34`
;  		vera_data_0_write(0x00);
;  	}
;  }
            ply
            ply
            sty     dp:.tiny (_Dp+14)
            ply
            sty     dp:.tiny (_Dp+12)
            ply
            sty     dp:.tiny (_Dp+8)
            rtl
`?L34`:     lda     ##0
            jsl     long:vera_data_0_write
            lda     1,s
            inc     a
            sta     1,s
            bra     `?L35`
;
;  void vera_reset(void) {
            .section farcode,text
            .public vera_reset
vera_reset:
;  	uint8_t ctrl = vera_ctrl_read();
            jsl     long:vera_ctrl_read
;  	vera_ctrl_write(ctrl | (1 << 7));
            ora     ##128
            jsl     long:vera_ctrl_write
;  }
            rtl
;
;  void vera_init(void) {
            .section farcode,text
            .public vera_init
vera_init:
;
;  	vera_mem_write(VERA_PALETTE_BASE, vera_palette, 0x200);
            ldx     ##0x200
            stx     dp:.tiny (_Dp+2)
            ldx     vera_palette
            stx     dp:.tiny _Dp
            lda     ##0xfa00
            ldx     ##1
            jsl     long:vera_mem_write
;  	vera_mem_write(TEXT_CONSOLE_TILES, vera_font_0, 0x1000);
            ldx     ##0x1000
            stx     dp:.tiny (_Dp+2)
            ldx     vera_font_0
            stx     dp:.tiny _Dp
            lda     ##0x800
            ldx     ##0
            jsl     long:vera_mem_write
;
;  	vera_dc_hscale_write(0x80);
            lda     ##128
            jsl     long:vera_dc_hscale_write
;  	vera_dc_vscale_write(0x80);
            lda     ##128
            jsl     long:vera_dc_vscale_write
;
;  	vera_dc_hstart_write(0);
            lda     ##0
            jsl     long:vera_dc_hstart_write
;  	vera_dc_hstop_write(640 >> 2);
            lda     ##160
            jsl     long:vera_dc_hstop_write
;  	vera_dc_vstart_write(0);
            lda     ##0
            jsl     long:vera_dc_vstart_write
;  	vera_dc_vstop_write(480 >> 1);
            lda     ##240
            jsl     long:vera_dc_vstop_write
;
;  	vera_l0_config_write(VERA_L_BPP1 | VERA_L_64H | VERA_L_128W);
            lda     ##96
            jsl     long:vera_l0_config_write
;  	vera_l0_mapbase_write(TEXT_CONSOLE0_VRAM >> 9);
            lda     ##12
            jsl     long:vera_l0_mapbase_write
;  	vera_l0_tilebase_write(((TEXT_CONSOLE_TILES >> 9) & 0b11111100) | VERA_TILESIZE8x16);
            lda     ##6
            jsl     long:vera_l0_tilebase_write
;  	vera_l0_hscroll_l_write(0);
            lda     ##0
            jsl     long:vera_l0_hscroll_l_write
;  	vera_l0_hscroll_h_write(0);
            lda     ##0
            jsl     long:vera_l0_hscroll_h_write
;  	vera_l0_vscroll_l_write(0);
            lda     ##0
            jsl     long:vera_l0_vscroll_l_write
;  	vera_l0_vscroll_h_write(0);
            lda     ##0
            jsl     long:vera_l0_vscroll_h_write
;
;  	vera_ien_write(0b00000000);
            lda     ##0
            jsl     long:vera_ien_write
;  	vera_isr_write(0b00000111);
            lda     ##7
            jsl     long:vera_isr_write
;  	vera_dc_video_write(0b00010001);
            lda     ##17
            jsl     long:vera_dc_video_write
;
;  	vera_mem_write(TEXT_CONSOLE0_VRAM, (void*)(0xC00000), 0x4000);
            ldx     ##0x4000
            stx     dp:.tiny (_Dp+2)
            ldx     ##0
            stx     dp:.tiny _Dp
            lda     ##0x1800
            ldx     ##0
            jsl     long:vera_mem_write
;  }
            rtl