2024-07-07 17:37:04 +02:00
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// SPDX-License-Identifier: MIT
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//
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// boot/w65c265s.h
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2024-07-08 05:08:08 +02:00
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// Defines for the W65C265S chip
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2024-07-07 17:37:04 +02:00
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//
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// Copyright © 2024 Kyle J Cardoza <Kyle.Cardoza@icloud.com>
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#define PD0 0x00DF00
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#define PD1 0x00DF01
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#define PD2 0x00DF02
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#define PD3 0x00DF03
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#define PD4 0x00DF20
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#define PD5 0x00DF21
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#define PD6 0x00DF22
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#define PD7 0x00DF23
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#define PDD0 0x00DF04
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#define PDD1 0x00DF05
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#define PDD2 0x00DF06
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#define PDD3 0x00DF07
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#define PDD4 0x00DF24
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#define PDD5 0x00DF25
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#define PDD6 0x00DF26
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#define PCS7 0x00DF27
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#define BCR 0x00DF40
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#define SSCR 0x00DF41
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#define TCR 0x00DF42
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#define TER 0x00DF43
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#define TIFR 0x00DF44
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#define EIFR 0x00DF45
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#define TIER 0x00DF46
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#define EIER 0x00DF47
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#define UIFR 0x00DF48
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#define UIER 0x00DF49
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#define T0LL 0x00DF50
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#define T0LH 0x00DF51
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#define T1LL 0x00DF52
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#define T1LH 0x00DF53
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#define T2LL 0x00DF54
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#define T2LH 0x00DF55
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#define T3LL 0x00DF56
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#define T3LH 0x00DF57
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#define T4LL 0x00DF58
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#define T4LH 0x00DF59
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#define T5LL 0x00DF5A
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#define T5LH 0x00DF5B
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#define T6LL 0x00DF5C
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#define T6LH 0x00DF5D
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#define T7LL 0x00DF5E
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#define T7LH 0x00DF5F
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#define T0CL 0x00DF60
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#define T0CH 0x00DF61
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#define T1CL 0x00DF62
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#define T1CH 0x00DF63
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#define T2CL 0x00DF64
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#define T2CH 0x00DF65
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#define T3CL 0x00DF66
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#define T3CH 0x00DF67
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#define T4CL 0x00DF68
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#define T4CH 0x00DF69
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#define T5CL 0x00DF6A
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#define T5CH 0x00DF6B
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#define T6CL 0x00DF6C
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#define T6CH 0x00DF6D
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#define T7CL 0x00DF6E
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#define T7CH 0x00DF6F
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#define ACSR0 0x00DF70
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#define ARTD0 0x00DF71
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#define ACSR1 0x00DF72
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#define ARTD1 0x00DF73
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#define ACSR2 0x00DF74
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#define ARTD2 0x00DF75
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#define ACSR3 0x00DF76
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#define ARTD3 0x00DF77
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#define PIBFR 0x00DF78
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#define PIBER 0x00DF79
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#define PIR2 0x00DF7A
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#define PIR3 0x00DF7B
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#define PIR4 0x00DF7C
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#define PIR5 0x00DF7D
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#define PIR6 0x00DF7E
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#define PIR7 0x00DF7F
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2024-07-08 05:08:08 +02:00
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#ifdef __CALYPSI_ASSEMBLER__
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2024-07-07 17:37:04 +02:00
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; Enable the 512 bytes of on-CPU SRAM from 0x000000-0001FF
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w65c265s_sram_on .macro
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lda #0b00000100
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trb SSCR
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.endm
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w65c265s_sram_off .macro
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lda #0b00000100
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tsb SSCR
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.endm
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; Disable the on-CPU ROM
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w65c265s_rom_off .macro
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lda #1 << 7
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tsb BCR
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.endm
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; Enable the on-CPU ROM
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w65c265s_rom_on .macro
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lda #1 << 7
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trb BCR
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.endm
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; Start FCLK
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fclk_start .macro
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lda #0b00000001
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tsb SSCR
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.endm
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; Stop FCLK
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fclk_stop .macro
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lda #0b00000001
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trb SSCR
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.endm
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; Select FCLK as the clock source
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fclk_select .macro
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lda #0b11111010
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tsb SSCR
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2024-07-08 05:08:08 +02:00
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.endm
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#endif
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