Fixed delay/crash issue -- you will need a power supply of at least 9V 2A to make it work properly.

src/boot.s

@@ -5,8 +5,11 @@
     jml w65c265s_init
 
 w65c265s_init .proc
-    ; Disable standard interrupts
+    ; Disable interrupts
     sei
+    stz UIER
+    stz TIER
+    stz EIER
     .short_a
     .long_i
 
@@ -40,10 +43,6 @@ delay_y
     ; Enable all the in-use chip select lines.
     lda #%11110011
     sta PCS7
-    
-    stz UIER
-    stz TIER
-    stz EIER
 
     ; Jump to entry point.
     jml main

src/irq.s

@@ -311,6 +311,9 @@ irq_init .proc
     lda #1 << 6
     tsb BCR
 
+    ; And enable normal IRQs.
+    cli
+
     .restore_registers
     rtl
 .endproc

src/vera.s

@@ -18,48 +18,22 @@ vera_init .proc
 vera_reset .proc
     .save_registers
 
-    ; Copy the routine to low memory
-    .memcpy $000100, vera_reset_low, size(vera_reset_low)
+    ; Pull the VERA /RES line low
+    lda #1 << 2
+    trb PD4
 
-    ; Call the copied routine
-    jsl $000100
+    ; Delay just a bit to make sure the reset takes effect.
+    ldx #10
+delay
+    dex
+    bne delay
 
-    .restore_registers
-    rtl
-.endproc
-
-; This is the routine that gets copied to on-CPU SRAM.
-vera_reset_low .proc
-    .logical $000100
-    .save_registers
-
-    ; If we get this far, we are in the CPU's on-chip SRAM, so the next step
-    ; is to disable the external address bus with BCR0 = 0
-    lda #%00000001
-    trb BCR
-
-    ; Now we let the FPGA configure itself by bringing its reset line high
-    ; with P4.2 = 1
+    ; Pull the VERA /RES line high
     lda #1 << 2
     tsb PD4
 
-    ; Now we delay a while as the FPGA re-combobulates itself.
-    ldx #150; Value dialed in by manual testing.
-delay_x
-    ldy #$FFFF
-delay_y
-    dey
-    bne delay_y
-    dex
-    bne delay_x
-
-    ; Before we return, we re-enable the external address bus with BCR0 = 1
-    lda #%00000001
-    tsb BCR
-
     .restore_registers
     rtl
-    .endlogical
 .endproc
 
 .endsection kernel